In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).

Fixes: 892df019 ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for rpmh clocks found in SM8150
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Convert the rpmh clock driver to use the new parent data scheme by
specifying the parent data for board clock.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.

[1]: https://lore.kernel.org/linux-arm-msm/20190830195142.103564-1-swboyd@chromium.org/Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.

Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: NDouglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: NStephen Boyd <swboyd@chromium.org>
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.orgReviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Extend the probe by index API in common code to be used
by other qcom clock controller.
Signed-off-by: NGovind Singh <govinds@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the WCSS QDSP gcc clock control used on qcs404
based devices. This would allow wcss remoteproc driver to control
the required gcc clocks to bring the subsystem out of reset.
Signed-off-by: NGovind Singh <govinds@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

QCOM_A53PLL and QCOM_CLK_APCS_MSM8916 stand out as the only options
built by default. Let's bring them back in line with the rest.
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Link: https://lkml.kernel.org/r/d654907d-a3a2-a00f-d6f5-3a34ae25ebcf@free.frReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: NDeepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and tidy-up
	port to new parent scheme
	Add comments for critical clocks]]
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-6-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Add programming sequence support for managing the Trion
PLLs.
Signed-off-by: NDeepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and tidy-up
	use upstream way of specifying PLLs]
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-4-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

We want users to code properly and fix the post_div_table missing and
not rely on core to check. So remove the post_div_table check.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-3-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Commit 8f9fab48 ("linux/kernel.h: fix overflow for
DIV_ROUND_UP_ULL") fixed the overflow for DIV_ROUND_UP_ULL, so we no
longer need the cast for DIV_ROUND_UP_ULL, so remove the unnecessary
u64 casts.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-2-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Clang produces the following warning

drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable]
static const struct
parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] =
{ ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static
const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^
drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map'
[-Wunused-const-variable] static const struct parent_map
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^
drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div'
[-Wunused-const-variable] static const char * const
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {

It looks like these were never used.

Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Cc: clang-built-linux@googlegroups.com
Link: https://github.com/ClangBuiltLinux/linux/issues/518Suggested-by: NNathan Chancellor <natechancellor@gmail.com>
Signed-off-by: NNathan Huckleberry <nhuck@google.com>
Reviewed-by: NNathan Chancellor <natechancellor@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Failing to toggle a GDSC as the driver core is attaching the
power-domain to a device will cause a silent probe deferral. Provide an
explicit warning to the developer, in order to reduce the amount of time
it takes to debug this.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NJeffrey Hugo <jhugo@codeaurora.org>
Tested-by: NJeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 and
  only version 2 as published by the free software foundation this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Based on 1 normalized pattern(s):

  this software is licensed under the terms of the gnu general public
  license version 2 as published by the free software foundation and
  may be copied distributed and modified under those terms this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 285 file(s).
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Reviewed-by: NAlexios Zavras <alexios.zavras@intel.com>
Reviewed-by: NAllison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.deSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

This patch corrects the SPDX License Identifier style
in clk-regmap-mux-div.h. For C header files
Documentation/process/license-rules.rst mandates C-like
comments (opposed to C source files where C++ style
should be used)

Changes made by using a script provided by Joe Perches here:
https://lkml.org/lkml/2019/2/7/46Suggested-by: NJoe Perches <joe@perches.com>
Signed-off-by: NNishad Kamdar <nishadkamdar@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

See similar issue solved by commit 5f2420ed
("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998")

Without this patch, PCIe PHY init fails:

qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16
phy phy-1c06000.phy.0: phy init failed --> -16
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Reviewed-by: NJeffrey Hugo <jhugo@codeaurora.org>
Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The Turing Clock Controller provides resources related to running the
Turing subsystem.

PM runtime is used to ensure that the associated AHB clock is ticking
while the clock framework is accessing the registers in the Turing clock
controller.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Some clocks can only be turned on by resetting the block containing
them, provide a clock type that allow us to reference these clocks and
have the client drivers enable and "disable" them.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add the clocks and resets need in order to control the Turing
remoteproc.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the
PHY, describe this relationship.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Several clock controller drivers define a list of clk_hw devices, and then
register those devices in probe() before using common code to process the
rest of initialization.  Extend the common code to accept a list of clk_hw
devices to process, thus eliminating many duplicate implementations.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Suggested-by: NStephen Boyd <sboyd@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Tested-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NAnu Ramanathan <anur@codeaurora.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The RCG CFG/M/N/D register base could be at a different offset than
the CMD register, so introduce a cfg_offset to identify the offset
with respect to the CMD RCGR register.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NAnu Ramanathan <anur@codeaurora.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Remove the redundant empty lines crept in.
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The clk-rpmh driver only supports on and off RPMh clock resources. Let's
extend the driver by adding support for clocks that are managed by a
different type of RPMh resource known as Bus Clock Manager(BCM). The BCM
is a configurable shared resource aggregator that scales performance
based on a set of frequency points. The Qualcomm IP Accelerator (IPA)
clock is an example of a resource that is managed by the BCM and this a
requirement from the IPA driver in order to scale its core clock.
Signed-off-by: NDavid Dai <daidavid1@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL
clock and needs to vote on the active only source of XO, so as to keep
the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has
the same requirement.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Fixes: 06391edd ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes
gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem.

gcc-msm8998: probe of 100000.clock-controller failed with error -38
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
for clients to vote on.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
the phy during init.  The clock needs to be enabled during the init
sequence, but may not be fully active until after the init sequence is
complete.  This causes a catch-22 if the clock status is checked during
enable.  As a result, skip the checks to avoid the troubling situation.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The usb30_master_clk supports a 60Mhz frequency, but that is missing from
the table of supported frequencies.  Add it.

Fixes: b5f5f525 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

A branch clock is basically a clock that can be gated for power savings,
but is also what devices/drivers consume.  Configuring a branch clock's
rate needs to be done at the source, so for all branch clocks which have
a defined parent, set CLK_SET_RATE_PARENT so that clk_set_rate() calls on
branch clocks can do what is expected.  This is important as most drivers
do not check the resulting clock rate after a successful clk_set_rate()
call, thus the driver may get out of sync with the actual hardware state
and weird issues might crop up.  This has been observed with issues
getting SDHCI to reliably support "fast" cards such as SDR104.

Fixes: 4807c71c (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

gcc_lpass_trig_clk is not used downstream, therefore there is no reason to
expect it to be needed for clients.  Let's remove it because messing with
the clock has been observed to cause Linux hangs when the qdss_clk is
initialized by rpmcc.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Fixes: 4807c71c (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be
disabled.  Any mmss access depends on this clock, and its been observed
that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit
access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is
disabled.
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Fixes: 4807c71c (arm64: dts: Add msm8998 SoC and MTP board support)
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

commit c0cb7c7e ("clk: qcom: Enumerate remaining msm8998 resets")
missed two USB2 resets.  Add them.

Fixes: c0cb7c7e ("clk: qcom: Enumerate remaining msm8998 resets")
Signed-off-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>