Signed-off-by: NMark Brown <broonie@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Currently the tegra slink driver acquires a runtime PM reference for the
duration of each transfer. This may result in the IP being powered down
between transfers which would be at best wasteful. Instead it is better
to do this in the callbacks that are generated before and after starting
a series of transfers, keeping the IP powered throughout.
Signed-off-by: NMark Brown <broonie@linaro.org>
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>

Use the wrapper functions for getting and setting the driver data using
platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev,
so we can directly pass a struct platform_device.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Neither tegra20_spi_cdata nor tegra30_spi_cdata are used outside this
file so they can, and should, be static.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Tegra only supports, and always enables, device tree. Remove all ifdefs
and runtime checks for DT support from the driver. Platform data is
therefore no longer required. Rework the driver to parse the device tree
directly into struct tegra_slink_data.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

There is no code to set spi->controller_data, and hence the HW CS logic
can never trigger. Remove the unused code.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This reverts commit faa98f7e which was
applied in error due to discussion ending up in the wrong thread.

Spi starts transfer using dma with DMA_CTRL_ACK which is not require
becasue spi driver does not use completed dma_desc after transfer
done and so it does not ack the dma descriptor. Removing the
DMA_CTRL_ACK flag to avoid memory leak in dma driver.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The variable bits_per_word is initialized but never used
otherwise, so remove the unused variable.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-By: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The prepare_transfer_hardware() is called in atomic context and
calling synchronous runtime pm calls can create scheduling deadlock.

Therefore, in place of calling runtime PM calls from prepare/unprepare
message transfer, calling this in transfer_one_message().
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

SPI core make sure that all transfer has proper speed set
before calling low level spi transfer. Hence, it is not
require to have check in spi driver.

Remove the check for speed validity from transfer and use it directly.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The spi core make sure that each transfer structure have the proper
setting for bits_per_word before calling low level transfer APIs.

Hence it is no more require to check again in low level driver for
this field whether this is set correct or not. Removing such code
from low level driver.

The txx9 change also removes a test for bits_per_word set to 0, and
forcing it to 8 in that case. This can also be removed now since
spi_setup() ensures spi->bits_per_word is not zero.

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Since Tegra spi devices do not have multiple clocks, no need to use
clock name to get the clock.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.

devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

CONFIG_HOTPLUG is going away as an option.  As result the __dev*
markings will be going away.

Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst,
and __devexit.

Bill Pemberton has done most of the legwork on this series. I've used
his script to purge the attributes from the drivers/gpio tree.
Reported-by: NBill Pemberton <wfp5p@virginia.edu>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Sequence compatible list for tegra20-slink driver to first
look for Tegra30 and then Tegra20. Tegra30 have additional
feature in HW which need to be utilize if it is provided from DT.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

When spi client does the spi transfer and does not sets
the bits_per_word for each transfer then set it as default
of spi device in spi core before calling low level transfer.

Removing the similar code from spi-tegra20-slink driver as
it is not required.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>