1. 17 9月, 2012 8 次提交
  2. 12 9月, 2012 1 次提交
  3. 10 9月, 2012 22 次提交
  4. 07 9月, 2012 5 次提交
  5. 05 9月, 2012 4 次提交
    • P
      powerpc/powernv: Always go into nap mode when CPU is offline · 375f561a
      Paul Mackerras 提交于
      The CPU hotplug code for the powernv platform currently only puts
      offline CPUs into nap mode if the powersave_nap variable is set.
      However, HV-style KVM on this platform requires secondary CPU threads
      to be offline and in nap mode.  Since we know nap mode works just
      fine on all POWER7 machines, and the only machines that support the
      powernv platform are POWER7 machines, this changes the code to
      always put offline CPUs into nap mode, regardless of powersave_nap.
      Powersave_nap still controls whether or not CPUs go into nap mode
      when idle, as before.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      375f561a
    • M
      powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int · 8b64a9df
      Mihai Caraman 提交于
      Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
      Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
      SPRG4-7 registers will be clobbered.
      For bolted TLB miss exception handlers, which is the version currently
      supported by KVM, use SPRN_SPRG_GEN_SCRATCH aka SPRG0 instead of
      SPRN_SPRG_TLB_SCRATCH aka SPRG6. Keep using TLB PACA slots to fit in one
      64-byte cache line.
      For critical exception handlers use SPRG3 instead of SPRG7. Provide a routine
      to store and restore user-visible SPRGs. This will be subsequently used
      to restore VDSO information in SPRG3. Add EX_R13 to paca slots to free up
      SPRG3 and change the critical exception epilog to use it.
      Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8b64a9df
    • M
      powerpc/booke64: Use GSRR registers in Guest Doorbell interrupts · 5473eb1c
      Mihai Caraman 提交于
      Guest Doorbell interrupts use guest save and restore registers. Add a new
      Guest Doorbell exception type to accommodate GSRR0/1 SPRs usage in exception
      prolog and fix the exception handler.
      Signed-off-by: NMihai Caraman <mihai.caraman@freescale.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      5473eb1c
    • A
      powerpc: Uprobes port to powerpc · 8b7b80b9
      Ananth N Mavinakayanahalli 提交于
      This is the port of uprobes to powerpc. Usage is similar to x86.
      
      [root@xxxx ~]# ./bin/perf probe -x /lib64/libc.so.6 malloc
      Added new event:
        probe_libc:malloc    (on 0xb4860)
      
      You can now use it in all perf tools, such as:
      
      	perf record -e probe_libc:malloc -aR sleep 1
      
      [root@xxxx ~]# ./bin/perf record -e probe_libc:malloc -aR sleep 20
      [ perf record: Woken up 22 times to write data ]
      [ perf record: Captured and wrote 5.843 MB perf.data (~255302 samples) ]
      [root@xxxx ~]# ./bin/perf report --stdio
      ...
      
          69.05%           tar  libc-2.12.so   [.] malloc
          28.57%            rm  libc-2.12.so   [.] malloc
           1.32%  avahi-daemon  libc-2.12.so   [.] malloc
           0.58%          bash  libc-2.12.so   [.] malloc
           0.28%          sshd  libc-2.12.so   [.] malloc
           0.08%    irqbalance  libc-2.12.so   [.] malloc
           0.05%         bzip2  libc-2.12.so   [.] malloc
           0.04%         sleep  libc-2.12.so   [.] malloc
           0.03%    multipathd  libc-2.12.so   [.] malloc
           0.01%      sendmail  libc-2.12.so   [.] malloc
           0.01%     automount  libc-2.12.so   [.] malloc
      
      The trap_nr addition patch is a prereq.
      Signed-off-by: NAnanth N Mavinakayanahalli <ananth@in.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8b7b80b9