1. 11 4月, 2017 6 次提交
  2. 08 2月, 2017 4 次提交
  3. 07 2月, 2017 1 次提交
  4. 26 1月, 2017 3 次提交
  5. 19 10月, 2016 1 次提交
  6. 19 9月, 2016 3 次提交
  7. 16 9月, 2016 8 次提交
  8. 30 8月, 2016 3 次提交
  9. 06 7月, 2016 7 次提交
    • S
      iwlwifi: pcie: centralize SCD status logging · 38398efb
      Sara Sharon 提交于
      Centralize the logging of SCD status. The motivation is
      that for a000 devices we will have new SCD HW, but this
      code was duplicate anyway, so it is a proper cleanup.
      Signed-off-by: NSara Sharon <sara.sharon@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      38398efb
    • S
      iwlwifi: pcie: load FW chunk for a000 devices · 564cdce7
      Sara Sharon 提交于
      Update the firmware load flow for TFH hardware.
      Signed-off-by: NSara Sharon <sara.sharon@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      564cdce7
    • E
      iwlwifi: pcie: fix a race in firmware loading flow · f16c3ebf
      Emmanuel Grumbach 提交于
      Upon firmware load interrupt (FH_TX), the ISR re-enables the
      firmware load interrupt only to avoid races with other
      flows as described in the commit below. When the firmware
      is completely loaded, the thread that is loading the
      firmware will enable all the interrupts to make sure that
      the driver gets the ALIVE interrupt.
      The problem with that is that the thread that is loading
      the firmware is actually racing against the ISR and we can
      get to the following situation:
      
      CPU0					CPU1
      iwl_pcie_load_given_ucode
      	...
      	iwl_pcie_load_firmware_chunk
      		wait_for_interrupt
      					<interrupt>
      					ISR handles CSR_INT_BIT_FH_TX
      					ISR wakes up the thread on CPU0
      	/* enable all the interrupts
      	 * to get the ALIVE interrupt
      	 */
      	iwl_enable_interrupts
      					ISR re-enables CSR_INT_BIT_FH_TX only
      	/* start the firmware */
      	iwl_write32(trans, CSR_RESET, 0);
      
      BUG! ALIVE interrupt will never arrive since it has been
      masked by CPU1.
      
      In order to fix that, change the ISR to first check if
      STATUS_INT_ENABLED is set. If so, re-enable all the
      interrupts. If STATUS_INT_ENABLED is clear, then we can
      check what specific interrupt happened and re-enable only
      that specific interrupt (RFKILL or FH_TX).
      
      All the credit for the analysis goes to Kirtika who did the
      actual debugging work.
      
      Cc: <stable@vger.kernel.org> [4.5+]
      Fixes: a6bd005f ("iwlwifi: pcie: fix RF-Kill vs. firmware load race")
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      f16c3ebf
    • J
      iwlwifi: decouple PCIe transport from mac80211 · 21cb3222
      Johannes Berg 提交于
      The PCIe transport needs to store two pointers in each TX SKB, and
      currently assumes mac80211's ieee80211_tx_info is present in the CB
      to do that.
      
      In order to remove that assumption, have the opmodes pass in the
      offset to where the pointers can be stored in the CB and use the
      offset in the PCIe code.
      
      To make the disentanglement complete, remove mac80211.h includes
      from everywhere in the generic iwlwifi code. This required adding
      an include of cfg80211.h in one place.
      Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      21cb3222
    • I
      iwlwifi: pcie: Enable MSI mode when using MSI interrupts · 54f315cb
      Ido Yariv 提交于
      On some of the chipsets MSI & INTA interrupts are disabled by default in
      the HW registers, and need to be explicitly enabled to be used.
      
      In case MSI-X isn't used, make sure MSI mode is enabled by setting
      the relevant HW register.
      Signed-off-by: NIdo Yariv <idox.yariv@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      54f315cb
    • E
      iwlwifi: pcie: enable interrupts before releasing the NIC's CPU · 2aabdbdc
      Emmanuel Grumbach 提交于
      The NIC's CPU gets started after the firmware has been
      written to its memory. The first thing it does is to
      send an interrupt to let the driver know that it is
      running. In order to get that interrupt, the driver needs
      to make sure it is not masked. Of course, the interrupt
      needs to be enabled in the driver before the CPU starts to
      run.
      I mistakenly inversed those two steps leading to races
      which prevented the driver from getting the alive interrupt
      from the firmware.
      Fix that.
      
      Cc: <stable@vger.kernel.org> [4.5+]
      Fixes: a6bd005f ("iwlwifi: pcie: fix RF-Kill vs. firmware load race")
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      2aabdbdc
    • L
      iwlwifi: mvm: support dqa queue sharing · 42db09c1
      Liad Kaufman 提交于
      Support DQA queue sharing when no free queue exists for
      allocation to a STA that already exists. This means that
      a single queue will serve more than a single TID (although
      the RA will be the same for all TIDs served).
      
      We try to choose the lowest AC possible, to ensure the
      shared queues have the lowest possible combined AC
      requirements. The queue to share is chosen only from the
      same RA's DATA queues as follows (in descending priority):
       1. An AC_BE queue
       2. Same AC queue
       3. Highest AC queue that is lower than new AC
       4. Any existing AC (there always is at least 1 DATA queue)
      
      If any aggregations existed for any of the TIDs of the
      shared queue - they are stopped (the FW is notified), but
      no delBA is sent.
      Signed-off-by: NLiad Kaufman <liad.kaufman@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      42db09c1
  10. 01 7月, 2016 1 次提交
    • S
      iwlwifi: pcie: workaround HW shadow registers bug · 1316d595
      Sara Sharon 提交于
      Integrated 9000 devices have a bug with shadow registers
      value retention.
      If driver writes RBD registers while MAC is asleep the
      values are stored in shadow registers to be copied whenever
      MAC wakes up.
      However, in 9000 devices a MAC wakeup is not triggered
      and when the bus powers down due to inactivity the shadow
      values and dirty bits are lost.
      Turn on the chicken-bits that cause MAC wakeup for RX-related
      values as well when the device is in D0.
      When the device is in low power mode turn the RX wakeup chicken
      bits off since driver is idle and this W/A is not needed.
      Remove previous W/A which was ineffective.
      Signed-off-by: NSara Sharon <sara.sharon@intel.com>
      Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
      1316d595
  11. 11 5月, 2016 3 次提交