1. 23 12月, 2015 2 次提交
  2. 11 5月, 2015 1 次提交
    • M
      powerpc/pasemi: Only the build the pasemi MSI code for PASEMI=y · 5af7a6f3
      Michael Ellerman 提交于
      The pasemi MSI code is currently always built when MPIC=y && PCI_MSI=y.
      It should not have any effect on other platforms, because it immediately
      checks the MPIC's compatible property for "pasemi,pwrficient-openpic".
      
      However it's odd that it's still built even when PASEMI=n. It also
      needn't be in sysdev, as it's only used by pasemi. So move it into
      platforms/pasemi, whereby it will only be built for PASEMI=y.
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      5af7a6f3
  3. 01 5月, 2014 1 次提交
  4. 19 2月, 2014 1 次提交
  5. 02 7月, 2013 2 次提交
  6. 08 5月, 2013 1 次提交
  7. 10 1月, 2013 2 次提交
  8. 03 1月, 2013 1 次提交
  9. 13 9月, 2012 1 次提交
    • V
      powerpc/mpic: FSL MPIC error interrupt support. · 0a408164
      Varun Sethi 提交于
      All SOC device error interrupts are muxed and delivered to the core
      as a single MPIC error interrupt. Currently all the device drivers
      requiring access to device errors have to register for the MPIC error
      interrupt as a shared interrupt.
      
      With this patch we add interrupt demuxing capability in the mpic driver,
      allowing device drivers to register for their individual error interrupts.
      This is achieved by handling error interrupts in a cascaded fashion.
      
      MPIC error interrupt is handled by the "error_int_handler", which
      subsequently demuxes it using the EISR and delivers it to the respective
      drivers.
      
      The error interrupt capability is dependent on the MPIC EIMR register,
      which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error
      interrupt demuxing capability is dependent on the MPIC version and can
      be used for versions >= 4.1.
      Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com>
      Signed-off-by: NBogdan Hamciuc <bogdan.hamciuc@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      0a408164
  10. 17 3月, 2012 2 次提交
  11. 05 1月, 2012 1 次提交
  12. 24 11月, 2011 1 次提交
  13. 23 9月, 2011 1 次提交
  14. 27 6月, 2011 1 次提交
    • A
      powerpc: introduce the ePAPR embedded hypervisor vmpic driver · 3a93261f
      Ashish Kalra 提交于
      The Freescale ePAPR reference hypervisor provides interrupt controller
      services via a hypercall interface, instead of emulating the MPIC
      controller.  This is called the VMPIC.
      
      The ePAPR "virtual interrupt controller" provides interrupt controller
      services for external interrupts.  External interrupts received by a
      partition can come from two sources:
      
        - Hardware interrupts - hardware interrupts come from external
          interrupt lines or on-chip I/O devices.
        - Virtual interrupts - virtual interrupts are generated by the hypervisor
          as part of some hypervisor service or hypervisor-created virtual device.
      
      Both types of interrupts are processed using the same programming model and
      same set of hypercalls.
      Signed-off-by: NAshish Kalra <ashish.kalra@freescale.com>
      Signed-off-by: NTimur Tabi <timur@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3a93261f
  15. 26 5月, 2011 1 次提交
  16. 20 4月, 2011 2 次提交
  17. 24 3月, 2011 1 次提交
  18. 29 11月, 2010 1 次提交
  19. 14 10月, 2010 1 次提交
  20. 13 10月, 2010 1 次提交
  21. 12 11月, 2009 1 次提交
  22. 17 6月, 2009 1 次提交
  23. 16 6月, 2009 1 次提交
    • M
      powerpc: Add configurable -Werror for arch/powerpc · ba55bd74
      Michael Ellerman 提交于
      Add the option to build the code under arch/powerpc with -Werror.
      
      The intention is to make it harder for people to inadvertantly introduce
      warnings in the arch/powerpc code. It needs to be configurable so that
      if a warning is introduced, people can easily work around it while it's
      being fixed.
      
      The option is a negative, ie. don't enable -Werror, so that it will be
      turned on for allyes and allmodconfig builds.
      
      The default is n, in the hope that developers will build with -Werror,
      that will probably lead to some build breaks, I am prepared to be flamed.
      
      It's not enabled for math-emu, which is a steaming pile of warnings.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ba55bd74
  24. 07 6月, 2009 1 次提交
  25. 31 12月, 2008 1 次提交
  26. 18 10月, 2008 1 次提交
  27. 13 10月, 2008 1 次提交
  28. 23 9月, 2008 1 次提交
  29. 20 8月, 2008 1 次提交
    • M
      powerpc: Split-out common MSI bitmap logic into msi_bitmap.c · 7e302869
      Michael Ellerman 提交于
      There are now two almost identical implementations of an MSI bitmap
      allocator, one in mpic_msi.c and the other in fsl_msi.c.
      
      Merge them together and put the result in msi_bitmap.c.  Some of the
      MPIC bits will remain to provide a nicer interface for the MPIC users.
      
      In the process we fix two buglets.  The first is that the allocation
      routines, now msi_bitmap_alloc_hwirqs(), returned an unsigned result,
      even though they use -1 to indicate allocation failure.  Although all
      the callers were checking correctly, it is much better for the routine
      to just return an int.  At least until someone wants > ~2 billion MSIs.
      
      The second buglet is that the device tree reservation logic only
      allowed power-of-two reservations.  AFAICT that didn't effect any
      existing code but it's nicer if we can reserve arbitrary irqs from MSI
      use.
      
      We also add some selftests, which exposed the two buglets and now test
      for them, as well as some basic sanity tests.  The tests are only built
      when CONFIG_DEBUG_KERNEL=y.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      7e302869
  30. 04 8月, 2008 1 次提交
  31. 11 6月, 2008 1 次提交
    • A
      powerpc/QE: switch to the cpm_muram implementation · 5093bb96
      Anton Vorontsov 提交于
      This is very trivial patch. We're transitioning to the cpm_muram_*
      calls. That's it.
      
      Less trivial changes:
      - BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines
        we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_*
        prototypes;
      - qe_muram_dump was unused and thus removed;
      - added some code to the cpm_common.c to support legacy QE bindings
        (data-only node name).
      - For convenience, define qe_* calls to cpm_*. So drivers need not to be
        changed.
      Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      5093bb96
  32. 10 6月, 2008 1 次提交
    • A
      powerpc/sysdev: implement FSL GTM support · 83ff9dcf
      Anton Vorontsov 提交于
      GTM stands for General-purpose Timers Module and able to generate
      timer{1,2,3,4} interrupts. These timers are used by the drivers that
      need time precise interrupts (like for USB transactions scheduling for
      the Freescale USB Host controller as found in some QE and CPM chips),
      or these timers could be used as wakeup events from the CPU deep-sleep
      mode.
      
      Things unimplemented:
      1. Cascaded (32 bit) timers (1-2, 3-4).
         This is straightforward to implement when needed, two timers should
         be marked as "requested" and configured as appropriate.
      2. Super-cascaded (64 bit) timers (1-2-3-4).
         This is also straightforward to implement when needed, all timers
         should be marked as "requested" and configured as appropriate.
      Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      83ff9dcf
  33. 03 6月, 2008 1 次提交
    • J
      [POWERPC] fsl: PCIe MSI support for 83xx/85xx/86xx processors. · 34e36c15
      Jason Jin 提交于
      This MSI driver can be used on 83xx/85xx/86xx board.
      In this driver, virtual interrupt host and chip were
      setup. There are 256 MSI interrupts in this host, Every 32
      MSI interrupts cascaded to one IPIC/MPIC interrupt.
      The chip was treated as edge sensitive and some necessary
      functions were setup for this chip.
      
      Before using the MSI interrupt, PCI/PCIE device need to
      ask for a MSI interrupt in the 256 MSI interrupts. A 256bit
      bitmap show which MSI interrupt was used, reserve bit in
      the bitmap can be used to force the device use some designate
      MSI interrupt in the 256 MSI interrupts. Sometimes this is useful
      for testing the all the MSI interrupts. The msi-available-ranges
      property in the dts file was used for this purpose.
      Signed-off-by: NJason Jin <Jason.jin@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      34e36c15
  34. 16 5月, 2008 1 次提交
  35. 17 4月, 2008 1 次提交