Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Tested-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

PHY transceiver driver for QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller present on
Qualcomm chipsets.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

We get the following compile errors if EXTCON is enabled as a
module but this driver is builtin:

drivers/built-in.o: In function `qcom_usb_hs_phy_power_off':
phy-qcom-usb-hs.c:(.text+0x1089): undefined reference to `extcon_unregister_notifier'
drivers/built-in.o: In function `qcom_usb_hs_phy_probe':
phy-qcom-usb-hs.c:(.text+0x11b5): undefined reference to `extcon_get_edev_by_phandle'
drivers/built-in.o: In function `qcom_usb_hs_phy_power_on':
phy-qcom-usb-hs.c:(.text+0x128e): undefined reference to `extcon_get_state'
phy-qcom-usb-hs.c:(.text+0x12a9): undefined reference to `extcon_register_notifier'

so let's mark this as needing to follow the modular status of
the extcon framework.

Fixes: 9994a338 e2427b09 (phy: Add support for Qualcomm's USB HS phy")
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This reverts commit d7bc1a7d ("phy: Add USB3 PHY support for
Broadcom NSP SoC") as we already have driver for this PHY (shared by NS
and NSP). It was added in commit e5666281 ("phy: bcm-ns-usb3: new
driver for USB 3.0 PHY on Northstar").

Instead of adding separated driver & duplicating code we should work on
improving existing (old) one. Thanks to work done by Broadcom we know
there is MDIO bus we weren't aware of & we know register names which
makes initialization more clear. This is very valuable info and we
should work on using it in existing driver afterwards.
Acked-by: NJon Mason <jon.mason@broadcom.com>
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>

Add support for Generic PHY framework about Exynos SoCs.  Current Exynos
PCIe driver doesn't use the PHY framework, which makes it difficult to
upstream the other Exynos variants because of different PHY registers.

Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
driver.

[bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update
copyright year, both per Vivek]
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>
Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Fix build errors in phy-rockchip-inno-usb2.c. The driver uses
extcon interfaces so it should depend on EXTCON.

Fixes these build errors:

drivers/built-in.o: In function `rockchip_usb2phy_otg_sm_work':
phy-rockchip-inno-usb2.c:(.text+0x2bcb): undefined reference to `extcon_get_state'
phy-rockchip-inno-usb2.c:(.text+0x2cd4): undefined reference to `extcon_set_state_sync'
phy-rockchip-inno-usb2.c:(.text+0x2cec): undefined reference to `extcon_set_state_sync'
phy-rockchip-inno-usb2.c:(.text+0x2d2d): undefined reference to `extcon_get_state'
drivers/built-in.o: In function `rockchip_usb2phy_probe':
phy-rockchip-inno-usb2.c:(.text+0x31d7): undefined reference to `extcon_get_edev_by_phandle'
phy-rockchip-inno-usb2.c:(.text+0x321a): undefined reference to `devm_extcon_dev_allocate'
phy-rockchip-inno-usb2.c:(.text+0x3230): undefined reference to `devm_extcon_dev_register'
phy-rockchip-inno-usb2.c:(.text+0x375a): undefined reference to `extcon_register_notifier'

Found in linux-next but is also needed in mainline.
Signed-off-by: NRandy Dunlap <rdunlap@infradead.org>
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for Broadcom NSP USB3 PHY
Signed-off-by: NYendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: <devicetree@vger.kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

When USB is disabled, we get a link error for this driver
because of the added OTG support

drivers/phy/phy-rockchip-inno-usb2.o: In function `rockchip_usb2phy_otg_sm_work':
phy-rockchip-inno-usb2.c:(.text.rockchip_usb2phy_otg_sm_work+0x1f4): undefined reference to `usb_otg_state_string'
drivers/phy/phy-rockchip-inno-usb2.o: In function `rockchip_usb2phy_probe':
phy-rockchip-inno-usb2.c:(.text.rockchip_usb2phy_probe+0x2c8): undefined reference to `of_usb_get_dr_mode_by_phy'

Other phy drivers select USB_COMMON for this, so let's do the same
here.

Fixes: 0c42fe48fd23 ("phy: rockchip-inno-usb2: support otg-port for rk3399")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

 documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

 documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The driver now calls of_usb_get_dr_mode_by_phy, which is part of the
USB core layer, and it fails to build when that is not provided:

drivers/phy/phy-sun4i-usb.o: In function `sun4i_usb_phy_probe':
phy-sun4i-usb.c:(.text.sun4i_usb_phy_probe+0x140): undefined reference to `of_usb_get_dr_mode_by_phy'

We already have a couple of other PHY drivers with a dependency
on USB_SUPPORT, so that seems to be the easiest fix here.

An alternative would be to adjust the #ifdef in include/linux/usb/of.h
to also check for CONFIG_USB_SUPPORT.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Fixes: b33ecca8 ("phy-sun4i-usb: Add support for peripheral-only mode")
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications.
The USB3 operates in SuperSpeed mode and the DP can operate at RBR,
HBR and HBR2 data rates. This driver create 2 PHY devices separately
for USB3 and DisplyPort, and registers them under the child node.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NGuenter Roeck <groeck@chromium.org>
Tested-by: NGuenter Roeck <groeck@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

On kernel builds without COMMON_CLK, the newly added rockchip-inno-usb2
driver fails to build:

drivers/phy/phy-rockchip-inno-usb2.c:124:16: error: field 'clk480m_hw'
has incomplete type
   struct clk_hw clk480m_hw;

In file included from include/linux/clk.h:16:0
                 from drivers/phy/phy-rockchip-inno-usb2.c:17:
include/linux/kernel.h:831:48: error: initialization from incompatible
pointer type [-Werror=incompatible-pointer-types]
   const typeof( ((type *)0)->member ) *__mptr = (ptr); \

  ... ...
Signed-off-by: NFrank Wang <frank.wang@rock-chips.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>

This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
than rk3288 and before, and most of phy-related registers are also
different from the past, so a new phy driver is required necessarily.
Signed-off-by: NFrank Wang <frank.wang@rock-chips.com>
Suggested-by: NHeiko Stuebner <heiko@sntech.de>
Suggested-by: NGuenter Roeck <linux@roeck-us.net>
Suggested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
This driver provides PHY init support in a generic way and can be bound
with XHCI controller driver.

There aren't any public datasheets from Broadcom so we can't have nice
defines for all used bits. It means we just follow Broadcom's
initialization procedure using their magic values. We were quite lucky
actually that Broadcom put some comments in their SDK reference code
explaining what given writes are responsible for.
Signed-off-by: NRafał Miłecki <rafal@milecki.pl>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0 PHY also allows overriding the VBUS and ID pins.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

instead of defining all functions as static inlines,
let's move them to udc-core and export them with
EXPORT_SYMBOL_GPL, that way we can make sure that
only GPL drivers will use them.

As a side effect, it'll be nicer to add tracepoints
to the gadget API.

While at that, also fix Kconfig dependencies to
avoid randconfig build failures.
Acked-By: NSebastian Reichel <sre@kernel.org>
Acked-by: NPeter Chen <peter.chen@nxp.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

Add PCI Phy support for Broadcom Northstar2 SoCs.  This driver uses the
interface from the iproc mdio mux driver to enable the devices
respective phys.
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NPramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
This driver provides PHY init support in a generic way and can be bound
with an EHCI controller driver.
There are (just a few) registers being defined in bcma header. It's
because DMU/CRU registers will be also needed in other drivers. We will
need them e.g. in PCIe controller/PHY driver and at some point probably
in clock driver for BCM53573 chipset. By using include/linux/bcma/ we
avoid code duplication.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a new OF device ID for mt2701

Some register settings to avoid RX sensitivity level degradation
which may arise on mt8173 platform are separated from other
platforms.
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds extcon support for otg related channel.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for Broadcom NS2 SATA3 PHY in existing
Broadcom SATA3 PHY driver.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs.
This hardware block used to be exposed as a pin controller, but it turns
out that this isn't a good fit. The new driver and DT binding much more
accurately describe the hardware and are more flexible in supporting new
SoC generations.
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Currently, we have a common SATA3 PHY driver for all Broadcom
STB SoCs. This driver can be extended and re-used for Broadcom
iProc SoCs having same SATA3 PHY.

This patch renames existing Broadcom STB SATA3 PHY driver to
common Broadcom SATA3 PHY driver to share this PHY driver across
Broadcom SoCs.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Make use of ARCH_RENESAS in place of ARCH_SHMOBILE.
A now redundant dependency on OF is also dropped.

This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The phy-am335x driver selects 'USB_COMMON', but all other drivers
use 'depends on' for that symbol, and it depends on USB || USB_GADGET
itself, which causes a Kconfig warning:

warning: (AM335X_PHY_USB) selects USB_COMMON which has unmet direct dependencies (USB_SUPPORT && (USB || USB_GADGET))

As suggested by Felipe Balbi, this turns the logic around, and makes
'USB_COMMON' selected by everything else that needs it, so we can
remove the dependencies.

Fixes: 59f042f6 ("usb: phy: phy-am335x: bypass first VBUS sensing for host-only mode")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NFelipe Balbi <balbi@kernel.org>
Reviewed-by: NPeter Chen <peter.chen@nxp.com>
Signed-off-by: NFelipe Balbi <felipe.balbi@linux.intel.com>

The phy-armada375-usb2 driver uses IOMEM functions so COMPILE_TEST && OF
build failed with:

drivers/built-in.o: In function `armada375_usb_phy_probe':
phy-armada375-usb2.c:(.text+0x121d): undefined reference to
`devm_ioremap_resource'
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The HiSilicon Hi6220 USB PHY is available in HiSilicon Hi6220 SoCs only.
Restrict it to HiSilicon arm64, unless compile-testing.
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
block for AHCI SATA3.

This new compatible string, "brcm,bcm7425-sata-phy", may be used for
most MIPS-based platforms of 40nm process technology.
Signed-off-by: NJaedon Shin <jaedon.shin@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Support hi6220 use phy for HiKey board
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device. And each channel has
independent registers about the PHYs.

So, the purpose of this driver is:
 1) initializes some registers of SoC specific to use the
    {ehci,ohci}-platform driver.

 2) detects id pin to select host or peripheral on the channel 0.

For now, this driver only supports 1) above.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The sun9i usb phy driver calls of_usb_get_phy_mode(), which is not
available if USB is disabled:

drivers/built-in.o: In function `sun9i_usb_phy_probe':
:(.text+0x7fb0): undefined reference to `of_usb_get_phy_mode'

This adds a dependency to avoid the randconfig build errors.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 9c3b4430 ("phy: Add driver to support individual USB PHYs on sun9i")
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
on Cygnus
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NArun Parameswaran <aparames@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

support usb3.0 phy of mt65xx SoCs
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>