The limitation of being able to check only for -EPROBE_DEFER from
dev_pm_domain_attach() has been removed. Hence let's respect all error
codes and bail out accordingly.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

We found the I2C controller count register is unreliable sometimes,
that will cause I2C to lose data. Thus we can read the data count
from 'i2c_dev->count' instead of the I2C controller count register.
Signed-off-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Add one flag to indicate if the i2c controller has been in suspend state,
which can prevent i2c accesses after i2c controller is suspended following
system suspend.
Signed-off-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

i2cdev_ioctl_rdwr() allocates i2c_msg.buf using memdup_user(), which
returns ZERO_SIZE_PTR if i2c_msg.len is zero.

Currently i2cdev_ioctl_rdwr() always dereferences the buf pointer in case
of I2C_M_RD | I2C_M_RECV_LEN transfer. That causes a kernel oops in
case of zero len.

Let's check the len against zero before dereferencing buf pointer.

This issue was triggered by syzkaller.
Signed-off-by: NAlexander Popov <alex.popov@linux.com>
Reviewed-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
[wsa: use '< 1' instead of '!' for easier readability]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Remove dependencies on HAS_DMA where a Kconfig symbol depends on another
symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST".
In most cases this other symbol is an architecture or platform specific
symbol, or PCI.

Generic symbols and drivers without platform dependencies keep their
dependencies on HAS_DMA, to prevent compiling subsystems or drivers that
cannot work anyway.

This simplifies the dependencies, and allows to improve compile-testing.
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: NMark Brown <broonie@kernel.org>
Acked-by: NRobin Murphy <robin.murphy@arm.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The API docs describe i2c_transfer() as taking a pointer to an array
of i2c_msg containing at least 1 entry, but leaves it to the individual
drivers to sanity check the msgs and num parameters. Let's do this in
core code instead.
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
[wsa: changed '<= 0' to '< 1']
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

On some systems, the BIOS expects certain SMBus register values to
match the hardware defaults. Restore these configuration registers at
shutdown time to avoid confusing the BIOS. This avoids hard-locking
such systems upon reboot.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Tested-by: NJason Andryuk <jandryuk@gmail.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@vger.kernel.org

Saving the original value of register SMBSLVCMD in
i801_enable_host_notify() doesn't work, because this function is
called not only at probe time but also at resume time. Do it in
i801_probe() instead, so that the saved value is not overwritten at
resume time.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Fixes: 22e94bd6 ("i2c: i801: store and restore the SLVCMD register at load and unload")
Reviewed-by: NBenjamin Tissoires <benjamin.tissoires@redhat.com>
Tested-by: NJason Andryuk <jandryuk@gmail.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@vger.kernel.org	# v4.10+

This is a cleaned up version of the I2C controller driver for
the Fujitsu F_I2C IP, which was never supported upstream, and
has now been incorporated into the Socionext SynQuacer SoC.
Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
[wsa: updated MAINTAINERS entry and removed two empty lines]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

No changes in refcount semantics -- key init is false; replace

static_key_slow_inc|dec   with   static_branch_inc|dec
static_key_false          with   static_branch_unlikely

Added a '_key' suffix to i2c_trace_msg, for better self
documentation.
Signed-off-by: NDavidlohr Bueso <dbueso@suse.de>
Reviewed-by: NDavid Howells <dhowells@redhat.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

According to the event i2c_result defined in include/trace/events/i2c.h,
the second parameter should be the number of messages instead of the
ended loop index. The value of ended loop index is the same as ret.
Signed-off-by: NAhbong Chang <cwahbong@google.com>
Reviewed-by: NTodd Poynor <toddpoynor@google.com>
Reviewed-by: NDavid Howells <dhowells@redhat.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This is unsafe, as the runtime PM callbacks are called from the PM
workqueue, so this may deadlock when handling an i2c attached clock,
which may already hold the clk_prepare mutex from another context.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Instead of repeatedly calling clk_get_rate for each transfer, register
a clock notifier to update the cached divider value each time the clock
rate actually changes.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Reviewed-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The blackfin architecture is getting removed, so the
twi driver can also be removed.
Acked-by: NAaron Wu <aaron.wu@analog.com>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

After previous refactoring, there is only one user in the same file
left. Make the function static now.

[wsa: added 'int' to bare 'unsigned']
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

According to documentation, Bit 7 of ICMSR is unused and 0 should be
written to it. Fix the mask accordingly.
Signed-off-by: NHiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
[wsa: edited commit message]
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Before assigning returned setup structure check if not null

Fixes: 463a9215 ("i2c: stm32f7: fix setup structure")
Signed-off-by: NPierre-Yves MORDRET <pierre-yves.mordret@st.com>
Acked-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org

Use device_property_read_u32 instead of of_property_read_u32_index to
lookup the "clock-frequency" property.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Allow for the reset-gpios property to be defined in the device tree
or via a GPIO lookup table.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Following are the major issues in current driver code

1. The current driver simply assumes the transfer completion
   whenever its gets any non-error interrupts and then simply do the
   polling of available/free bytes in FIFO.
2. The block mode is not working properly since no handling in
   being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_READ.
3. An i2c transfer can contain multiple message and QUP v2
   supports reconfiguration during run in which the mode should be same
   for all the sub transfer. Currently the mode is being programmed
   before every sub transfer which is functionally wrong. If one message
   is less than FIFO length and other message is greater than FIFO
   length, then transfers will fail.

Because of above, i2c v2 transfers of size greater than 64 are failing
with following error message

	i2c_qup 78b6000.i2c: timeout for fifo out full

To make block mode working properly and move to use the interrupts
instead of polling, major code reorganization is required. Following
are the major changes done in this patch

1. Remove the polling of TX FIFO free space and RX FIFO available
   bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
   QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
   interrupts to handle FIFO’s properly so check all these interrupts.
2. Determine the mode for transfer before starting by checking
   all the tx/rx data length in each message. The complete message can be
   transferred either in DMA mode or Programmed IO by FIFO/Block mode.
   in DMA mode, both tx and rx uses same mode but in PIO mode, the TX and
   RX can be in different mode.
3. During write, For FIFO mode, TX FIFO can be directly written
   without checking for FIFO space. For block mode, the QUP will generate
   OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
   space.
4. During read, both TX and RX FIFO will be used. TX will be used
   for writing tags and RX will be used for receiving the data. In QUP,
   TX and RX can operate in separate mode so configure modes accordingly.
5. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
   will be generated after all the bytes have been copied in RX FIFO. For
   read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
   whenever it has block size of available data.
6. Split the transfer in chunk of one QUP block size(256 bytes)
   and schedule each block separately. QUP v2 supports reconfiguration
   during run in which QUP can transfer multiple blocks without issuing a
   stop events.
7. Port the SMBus block read support for new code changes.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Following are the major issues in current driver code

1. The current driver simply assumes the transfer completion
   whenever its gets any non-error interrupts and then simply do the
   polling of available/free bytes in FIFO.
2. The block mode is not working properly since no handling in
   being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ.

Because of above, i2c v1 transfers of size greater than 32 are failing
with following error message

	i2c_qup 78b6000.i2c: timeout for fifo out full

To make block mode working properly and move to use the interrupts
instead of polling, major code reorganization is required. Following
are the major changes done in this patch

1. Remove the polling of TX FIFO free space and RX FIFO available
   bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
   QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
   interrupts to handle FIFO’s properly so check all these interrupts.
2. During write, For FIFO mode, TX FIFO can be directly written
   without checking for FIFO space. For block mode, the QUP will generate
   OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
   space.
3. During read, both TX and RX FIFO will be used. TX will be used
   for writing tags and RX will be used for receiving the data. In QUP,
   TX and RX can operate in separate mode so configure modes accordingly.
4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
   will be generated after all the bytes have been copied in RX FIFO. For
   read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
   whenever it has block size of available data.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

According to I2c specification, “If a master-receiver sends a
repeated START condition, it sends a not-acknowledge (A) just
before the repeated START condition”. QUP v2 supports sending
of NACK without stop with QUP_TAG_V2_DATARD_NACK so added the
same.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The BAM mode requires buffer for start tag data and tx, rx SG
list. Currently, this is being taken for maximum transfer length
(65K). But an I2C transfer can have multiple messages and each
message can be of this maximum length so the buffer overflow will
happen in this case. Since increasing buffer length won’t be
feasible since an I2C transfer can contain any number of messages
so this patch does following changes to make i2c transfers working
for multiple messages case.

1. Calculate the required buffers for 2 maximum length messages
   (65K * 2).
2. Split the descriptor formation and descriptor scheduling.
   The idea is to fit as many messages in one DMA transfers for 65K
   threshold value (max_xfer_sg_len). Whenever the sg_cnt is
   crossing this, then schedule the BAM transfer and subsequent
   transfer will again start from zero.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Currently the completion timeout is being taken according to
maximum transfer length which is too high if SCL is operating in
high frequency. This patch calculates timeout on the basis of
one-byte transfer time and uses the same for completion timeout.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Currently each message length in complete transfer is being
checked for determining DMA mode and if any of the message length
is less than FIFO length then non DMA mode is being used which
will increase overhead. DMA can be used for any length and it
should be determined with complete transfer length. Now, this
patch selects DMA mode if the total length is greater than FIFO
length.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Currently the i2c error handling in BAM mode is not working
properly in stress condition.

1. After an error, the FIFO are being written with FLUSH and
   EOT tags which should not be required since already these tags
   have been written in BAM descriptor itself.

2. QUP state is being moved to RESET in IRQ handler in case
   of error. When QUP HW encounters an error in BAM mode then it
   moves the QUP STATE to PAUSE state. In this case, I2C_FLUSH
   command needs to be executed while moving to RUN_STATE by writing
   to the QUP_STATE register with the I2C_FLUSH bit set to 1.

3. In Error case, sometimes, QUP generates more than one
   interrupt which will trigger the complete again. After an error,
   the flush operation will be scheduled after doing
   reinit_completion which should be triggered by BAM IRQ callback.
   If the second QUP IRQ comes during this time then it will call
   the complete and the transfer function will assume the all the
   BAM HW descriptors have been completed.

4. The release DMA is being called after each error which
   will free the DMA tx and rx channels. The error like NACK is very
   common in I2C transfer and every time this will be overhead. Now,
   since the error handling is proper so this release channel can be
   completely avoided.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

In case of FLUSH operation, BAM copies INPUT EOT FLUSH (0x94)
instead of normal EOT (0x93) tag in input data stream when an
input EOT tag is received during flush operation. So only one tag
will be written instead of 2 separate tags.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The role of FLUSH and EOT tag is to flush already scheduled
descriptors in BAM HW in case of error. EOT is required only
when descriptors are scheduled in RX FIFO. If all the messages
are WRITE, then only FLUSH tag will be used.

A single BAM transfer can have multiple read and write messages.
The EOT and FLUSH tags should be scheduled at the end of BAM HW
descriptors. Since the READ and WRITE can be present in any order
so for some of the cases, these tags are not being written
correctly.

Following is one of the example

   READ, READ, READ, READ

Currently EOT and FLUSH tags are being written after each READ.
If QUP gets NACK for first READ itself, then flush will be
triggered. It will look for first FLUSH tag in TX FIFO and will
stop there so only descriptors for first READ descriptors be
flushed. All the scheduled descriptors should be cleared to
generate BAM DMA completion.

Now this patch is scheduling FLUSH and EOT only once after all the
descriptors. So, flush will clear all the scheduled descriptors and
BAM will generate the completion interrupt.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The rx_nents and tx_nents are redundant. rx_buf and tx_buf can
be used for total number of SG entries. Since rx_buf and tx_buf
give the impression that it is buffer instead of count so rename
it to tx_cnt and rx_cnt for giving it more meaningful variable
name.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

1. Assigns use_dma in qup_dev structure itself which will
   help in subsequent patches to determine the mode in IRQ handler.
2. Does minor code reorganization for loops to reduce the
   unnecessary comparison and assignment.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The QUP BSLP BAM generates the following error sometimes if the
current I2C DMA transfer fails and the flush operation has been
scheduled

    “bam-dma-engine 7884000.dma: Cannot free busy channel”

If any I2C error comes during BAM DMA transfer, then the QUP I2C
interrupt will be generated and the flush operation will be
carried out to make I2C consume all scheduled DMA transfer.
Currently, the same completion structure is being used for BAM
transfer which has already completed without reinit. It will make
flush operation wait_for_completion_timeout completed immediately
and will proceed for freeing the DMA resources where the
descriptors are still in process.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Acked-by: NSricharan R <sricharan@codeaurora.org>
Reviewed-by: NAustin Christ <austinwc@codeaurora.org>
Reviewed-by: NAndy Gross <andy.gross@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The file has been updated from 2016 to 2018 so fixed the
copyright years.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

In case we receive NACK on DATA we shouldn't be resetting the controller,
rather we should issue STOP command. This will terminate the current
transaction and -EIO is returned.

While at that handle the SMBus Quick Command properly.
We shouldn't be setting the XLP9XX_I2C_CMD_READ/WRITE for such
transactions.
Signed-off-by: NGeorge Cherian <george.cherian@cavium.com>
Reviewed-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

I2C bus enters the STOP condition after the DATA_DONE interrupt is raised.
Essentially the driver should be checking the bus state before sending
any transaction. In case a transaction is initiated while the
bus is busy, the prior transaction's stop condition is not achieved.
Add the check to make sure the bus is not busy before every transaction.
Signed-off-by: NGeorge Cherian <george.cherian@cavium.com>
Reviewed-by: NJan Glauber <jglauber@cavium.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The hardware may not support SDA hold time configuration, but if it is
not set in the Device Tree either, there is no need to print a warning.
Reported-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NAlexander Monakov <amonakov@ispras.ru>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The errata FE-8471889 description has been updated. There is still a
timing violation for repeated start. But the errata now states that it
was only the case for the Standard mode (100 kHz), in Fast mode (400 kHz)
there is no issue.

This patch limit the errata fix to the Standard mode.

It has been tesed successfully on the clearfog (Aramda 388 based board).
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Suspend functions seem to have been copied from i2c-cadence driver.
Rename the functions to match the rest of the driver.
Signed-off-by: NMoritz Fischer <mdf@kernel.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Make sure to not disallow the chips on adapters that are not capable
of reading the device id, but also make sure to check the device id
before writing to the chip.
Tested-by: NAdrian Fiergolski <adrian.fiergolski@cern.ch>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Can be used during probe to double check that the probed device is
what is expected.

Loosely based on code from Adrian Fiergolski <adrian.fiergolski@cern.ch>.
Tested-by: NAdrian Fiergolski <adrian.fiergolski@cern.ch>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Signed-off-by: NPeter Rosin <peda@axentia.se>

Now that arch/metag/ has been removed, remove the METAG dependency from
the IMG SCB I2C device driver. The hardware is also present on MIPS SoCs
so the driver still has value.
Signed-off-by: NJames Hogan <jhogan@kernel.org>
Acked-by: NWolfram Sang <wsa@the-dreams.de>
Cc: linux-i2c@vger.kernel.org
Cc: linux-metag@vger.kernel.org