1. 12 8月, 2022 1 次提交
  2. 23 5月, 2022 3 次提交
    • I
      dpaa2-eth: unmap the SGT buffer before accessing its contents · 0a09c5b8
      Ioana Ciornei 提交于
      DMA unmap the Scatter/Gather table before going through the array to
      unmap and free each of the header and data chunks. This is so we do not
      touch the data between the dma_map and dma_unmap calls.
      
      Fixes: 3dc709e0 ("dpaa2-eth: add support for software TSO")
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0a09c5b8
    • I
      dpaa2-eth: use the correct software annotation field · d5f4e19a
      Ioana Ciornei 提交于
      The incorrect software annotation field was being used, swa->sg.sgt_size
      instead of swa->tso.sgt_size, which meant that the SGT buffer was
      unmapped with a wrong size.
      This is also confirmed by the DMA API debug prints which showed the
      following:
      
      [   38.962434] DMA-API: fsl_dpaa2_eth dpni.2: device driver frees DMA memory with different size [device address=0x0000fffffafba740] [map size=224 bytes] [unmap size=0 bytes]
      [   38.980496] WARNING: CPU: 11 PID: 1131 at kernel/dma/debug.c:973 check_unmap+0x58c/0x9b0
      [   38.988586] Modules linked in:
      [   38.991631] CPU: 11 PID: 1131 Comm: iperf3 Not tainted 5.18.0-rc7-00117-g59130eeb2b8f #1972
      [   38.999970] Hardware name: NXP Layerscape LX2160ARDB (DT)
      
      Fixes: 3dc709e0 ("dpaa2-eth: add support for software TSO")
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d5f4e19a
    • I
      dpaa2-eth: retrieve the virtual address before dma_unmap · 06d12994
      Ioana Ciornei 提交于
      The TSO header was DMA unmapped before the virtual address was retrieved
      and then used to free the buffer. This meant that we were actually
      removing the DMA map and then trying to search for it to help in
      retrieving the virtual address. This lead to a invalid virtual address
      being used in the kfree call.
      
      Fix this by calling dpaa2_iova_to_virt() prior to the dma_unmap call.
      
      [  487.231819] Unable to handle kernel paging request at virtual address fffffd9807000008
      
      (...)
      
      [  487.354061] Hardware name: SolidRun LX2160A Honeycomb (DT)
      [  487.359535] pstate: a0400005 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
      [  487.366485] pc : kfree+0xac/0x304
      [  487.369799] lr : kfree+0x204/0x304
      [  487.373191] sp : ffff80000c4eb120
      [  487.376493] x29: ffff80000c4eb120 x28: ffff662240c46400 x27: 0000000000000001
      [  487.383621] x26: 0000000000000001 x25: ffff662246da0cc0 x24: ffff66224af78000
      [  487.390748] x23: ffffad184f4ce008 x22: ffffad1850185000 x21: ffffad1838d13cec
      [  487.397874] x20: ffff6601c0000000 x19: fffffd9807000000 x18: 0000000000000000
      [  487.405000] x17: ffffb910cdc49000 x16: ffffad184d7d9080 x15: 0000000000004000
      [  487.412126] x14: 0000000000000008 x13: 000000000000ffff x12: 0000000000000000
      [  487.419252] x11: 0000000000000004 x10: 0000000000000001 x9 : ffffad184d7d927c
      [  487.426379] x8 : 0000000000000000 x7 : 0000000ffffffd1d x6 : ffff662240a94900
      [  487.433505] x5 : 0000000000000003 x4 : 0000000000000009 x3 : ffffad184f4ce008
      [  487.440632] x2 : ffff662243eec000 x1 : 0000000100000100 x0 : fffffc0000000000
      [  487.447758] Call trace:
      [  487.450194]  kfree+0xac/0x304
      [  487.453151]  dpaa2_eth_free_tx_fd.isra.0+0x33c/0x3e0 [fsl_dpaa2_eth]
      [  487.459507]  dpaa2_eth_tx_conf+0x100/0x2e0 [fsl_dpaa2_eth]
      [  487.464989]  dpaa2_eth_poll+0xdc/0x380 [fsl_dpaa2_eth]
      
      Fixes: 3dc709e0 ("dpaa2-eth: add support for software TSO")
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=215886Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      06d12994
  3. 14 3月, 2022 1 次提交
    • I
      dpaa2-mac: configure the SerDes phy on a protocol change · f978fe85
      Ioana Ciornei 提交于
      This patch integrates the dpaa2-eth driver with the generic PHY
      infrastructure in order to search, find and reconfigure the SerDes lanes
      in case of a protocol change.
      
      On the .mac_config() callback, the phy_set_mode_ext() API is called so
      that the Lynx 28G SerDes PHY driver can change the lane's configuration.
      In the same phylink callback the MC firmware is called so that it
      reconfigures the MAC side to run using the new protocol.
      
      The consumer drivers - dpaa2-eth and dpaa2-switch - are updated to call
      the dpaa2_mac_start/stop functions newly added which will
      power_on/power_off the associated SerDes lane.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f978fe85
  4. 20 2月, 2022 1 次提交
    • R
      dpaa2-eth: Update SINGLE_STEP register access · c4680c97
      Radu Bulie 提交于
      DPAA2 MAC supports 1588 one step timestamping.
      If this option is enabled then for each transmitted PTP event packet,
      the 1588 SINGLE_STEP register is accessed to modify the following fields:
      
      -offset of the correction field inside the PTP packet
      -UDP checksum update bit,  in case the PTP event packet has
       UDP encapsulation
      
      These values can change any time, because there may be multiple
      PTP clients connected, that receive various 1588 frame types:
      - L2 only frame
      - UDP / Ipv4
      - UDP / Ipv6
      - other
      
      The current implementation uses dpni_set_single_step_cfg to update the
      SINLGE_STEP register.
      Using an MC command  on the Tx datapath for each transmitted 1588 message
      introduces high delays, leading to low throughput and consequently to a
      small number of supported PTP clients. Besides these, the nanosecond
      correction field from the PTP packet will contain the high delay from the
      driver which together with the originTimestamp will render timestamp
      values that are unacceptable in a GM clock implementation.
      
      This patch updates the Tx datapath for 1588 messages when single step
      timestamp is enabled and provides direct access to SINGLE_STEP register,
      eliminating the  overhead caused by the dpni_set_single_step_cfg
      MC command. MC version >= 10.32 implements this functionality.
      If the MC version does not have support for returning the
      single step register base address, the driver will use
      dpni_set_single_step_cfg command for updates operations.
      
      All the delay introduced by dpni_set_single_step_cfg
      function will be eliminated (if MC version has support for returning the
      base address of the single step register), improving the egress driver
      performance for PTP packets when single step timestamping is enabled.
      
      Before these changes the maximum throughput for 1588 messages with
      single step hardware timestamp enabled was around 2000pps.
      After the updates the throughput increased up to 32.82 Mbps / 46631.02 pps.
      Signed-off-by: NRadu Bulie <radu-andrei.bulie@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c4680c97
  5. 15 2月, 2022 2 次提交
  6. 10 2月, 2022 1 次提交
  7. 09 2月, 2022 6 次提交
    • I
      dpaa2-eth: add support for software TSO · 3dc709e0
      Ioana Ciornei 提交于
      This patch adds support for driver level TSO in the enetc driver using
      the TSO API.
      
      There is not much to say about this specific implementation. We are
      using the usual tso_build_hdr(), tso_build_data() to create each data
      segment, we create an array of S/G FDs where the first S/G entry is
      referencing the header data and the remaining ones the data portion.
      
      For the S/G Table buffer we use the same cache of buffers used on the
      other non-GSO cases - dpaa2_eth_sgt_get() and dpaa2_eth_sgt_recycle().
      
      We cannot keep a DMA coherent buffer for all the TSO headers because the
      DPAA2 architecture does not work in a ring based fashion so we just
      allocate a buffer each time.
      
      Even with these limitations we get the following improvement in TCP
      termination on the LX2160A SoC, on a single A72 core running at 2.2GHz.
      
      before: 6.38Gbit/s
      after:  8.48Gbit/s
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3dc709e0
    • I
      dpaa2-eth: work with an array of FDs · a4ca448e
      Ioana Ciornei 提交于
      Up until now, the __dpaa2_eth_tx function used a single FD on the stack
      to construct the structure to be enqueued. Since we are now preparing
      the ground work to add support for TSO done in software at the driver
      level, the same function needs to work with an array of FDs and enqueue
      as many as the build_*_fd functions create.
      
      Make the necessary adjustments in order to do this. These include:
      keeping an array of FDs in a percpu structure, cleaning up the necessary
      FDs before populating it and then, retrying the enqueue process up till
      all the generated FDs were enqueued or until we reach the maximum number
      retries.
      
      This patch does not change the fact that only a single FD will result
      from a __dpaa2_eth_tx call but rather just creates the necessary changes
      for the next patch.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a4ca448e
    • I
      dpaa2-eth: use the S/G table cache also for the normal S/G path · a4218aef
      Ioana Ciornei 提交于
      Instead of allocating memory for an S/G table each time a nonlinear skb
      is processed, and then freeing it on the Tx confirmation path, use the
      S/G table cache in order to reuse the memory.
      
      For this to work we have to change the size of the cached buffers so
      that it can hold the maximum number of scatterlist entries.
      
      Other than that, each allocate/free call is replaced by a call to the
      dpaa2_eth_sgt_get/dpaa2_eth_sgt_recycle functions, introduced in the
      previous patch.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a4218aef
    • I
      dpaa2-eth: extract the S/G table buffer cache interaction into functions · ae3b0817
      Ioana Ciornei 提交于
      The dpaa2-eth driver uses in certain circumstances a buffer cache for
      the S/G tables needed in case of a S/G FD. At the moment, the
      interraction with the cache is open-coded and couldn't be reused easily.
      
      Add two new functions - dpaa2_eth_sgt_get and dpaa2_eth_sgt_recycle -
      which help with code reusability.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ae3b0817
    • I
      dpaa2-eth: allocate a fragment already aligned · 8378a791
      Ioana Ciornei 提交于
      Instead of allocating memory and then manually aligning it to the
      desired value use napi_alloc_frag_align() directly to streamline the
      process.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8378a791
    • I
      dpaa2-eth: rearrange variable declaration in __dpaa2_eth_tx · 035dd64d
      Ioana Ciornei 提交于
      In the next patches we'll be moving things arroung in the mentioned
      function and also add some new variable declarations. Before all this,
      cleanup the variable declaration order.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      035dd64d
  8. 17 12月, 2021 1 次提交
  9. 14 12月, 2021 1 次提交
  10. 30 11月, 2021 1 次提交
  11. 17 11月, 2021 1 次提交
  12. 15 10月, 2021 1 次提交
    • I
      net: dpaa2: add adaptive interrupt coalescing · fc398bec
      Ioana Ciornei 提交于
      Add support for adaptive interrupt coalescing to the dpaa2-eth driver.
      First of all, ETHTOOL_COALESCE_USE_ADAPTIVE_RX is defined as a supported
      coalesce parameter and the requested state is configured through the
      dpio APIs added in the previous patch.
      
      Besides the ethtool API interaction, we keep track of how many bytes and
      frames are dequeued per CDAN (Channel Data Availability Notification)
      and update the Net DIM instance through the dpaa2_io_update_net_dim()
      API.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fc398bec
  13. 05 10月, 2021 1 次提交
  14. 27 9月, 2021 1 次提交
  15. 04 8月, 2021 1 次提交
  16. 28 7月, 2021 1 次提交
    • A
      dev_ioctl: split out ndo_eth_ioctl · a7605370
      Arnd Bergmann 提交于
      Most users of ndo_do_ioctl are ethernet drivers that implement
      the MII commands SIOCGMIIPHY/SIOCGMIIREG/SIOCSMIIREG, or hardware
      timestamping with SIOCSHWTSTAMP/SIOCGHWTSTAMP.
      
      Separate these from the few drivers that use ndo_do_ioctl to
      implement SIOCBOND, SIOCBR and SIOCWANDEV commands.
      
      This is a purely cosmetic change intended to help readers find
      their way through the implementation.
      
      Cc: Doug Ledford <dledford@redhat.com>
      Cc: Jason Gunthorpe <jgg@ziepe.ca>
      Cc: Jay Vosburgh <j.vosburgh@gmail.com>
      Cc: Veaceslav Falico <vfalico@gmail.com>
      Cc: Andy Gospodarek <andy@greyhouse.net>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Vivien Didelot <vivien.didelot@gmail.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Vladimir Oltean <olteanv@gmail.com>
      Cc: Leon Romanovsky <leon@kernel.org>
      Cc: linux-rdma@vger.kernel.org
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NJason Gunthorpe <jgg@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a7605370
  17. 25 6月, 2021 1 次提交
  18. 22 5月, 2021 1 次提交
  19. 03 4月, 2021 3 次提交
  20. 18 3月, 2021 1 次提交
  21. 12 2月, 2021 1 次提交
  22. 07 2月, 2021 2 次提交
  23. 14 1月, 2021 2 次提交
  24. 10 1月, 2021 3 次提交
  25. 09 1月, 2021 2 次提交