ACR LS FW loading is moving out of SECBOOT and into their specific subdevs,
and the available GP108/GV100 FWs differ from the other GP10x boards.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This will allow us to register the falcon with ACR, and further customise
its behaviour by providing the nvkm_falcon_func structure directly.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This will allow for further customisation of the subdev depending on what
firmware is available.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

ACR LS FW loading is moving out of SECBOOT and into their specific subdevs,
and the available GP107/GP108 FWs have interface differences.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

It serves the exact same purpose.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

ACR LS FW loading is moving out of SECBOOT and into their specific subdevs,
and the available GM20B/GP10B FWs have interface differences.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

PMU, SEC2 and GR will be modified to register their falcons with ACR before
the main commit switching everything over.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This will replace the current SECBOOT subdev for handling firmware on
secure falcons.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Will be used as a basis for implementing changes needed for Turing.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Method init is typically ordered by class in the FW image as ThreeD,
TwoD, Compute.

Due to a bug in parsing the FW into our internal format, we've been
accidentally sending Twod + Compute methods to the ThreeD class, as
well as Compute methods to the TwoD class - oops.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

gp10b uses the new engine enumeration mechanism introduced in the Pascal
architecture. As a result, the copy engine, which used to be at index 2
for prior Tegra GPU instantiations, has now moved to index 0. Fix up the
index and also use the gp100 variant of the copy engine class because on
gp10b the PASCAL_DMA_COPY_B class is not supported.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

If the GPU clock has not had a rate set, initialize it to the maximum
clock rate to make sure it does run.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.

On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the power-ungate procedure can cause the GPU to go
into a bad state where the memory interface can no longer access system
memory.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

There is no BAR2 on GP10B and there is no need to map through BAR2
because all memory is shared between the GPU and the CPU. Add a custom
implementation of the fault sub-device that uses nvkm_memory_addr()
instead of nvkm_memory_bar2() to return the address of a pinned fault
buffer.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Commit 5fde30a2684041f9820aa9dc4fbd0009a45076a9 in envytools modified
some of the Falcon V5 encodings, regenerate the relevant FW with this.

Also modify build rules to include SPDX header in generated files.

Tested on GM107, with no issues noted.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Pascal was particularly incorrect, as the register changed to be more in the
same format as the MMU fault buffers are.

Shouldn't have impacted much more than confusing MMU fault log messages.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Would like to be able to reuse gf100_fifo_intr_fault() for (some of) the
later chipsets too, as it's identical.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

The bulk SPDX addition made all these files into GPL-2.0 licensed files.
However the remainder of the project is MIT-licensed, these files
were simply missing the boiler plate and got caught up in the global update.

Fixes: 96ac6d43 (treewide: Add SPDX license identifier - Kbuild)
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

The bulk SPDX addition made all these files into GPL-2.0 licensed files.
However the remainder of the project is MIT-licensed, these files
(primarily header files) were simply missing the boiler plate and got
caught up in the global update.

Fixes: b2441318 (License cleanup: add SPDX GPL-2.0 license identifier to files with no license)
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Acked-by: NEmil Velikov <emil.l.velikov@gmail.com>
Acked-by: NKarol Herbst <kherbst@redhat.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Regs seem valid here still, and tested on TU116.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing
graphics/compute bring-up.

Each subsystem was compared with traces, along with various tests to check
that things generally work as they should, and appears compatible enough
with the current TU117 code to enable support.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Fix a crash or broken depth testing in all OpenGL applications that use the
depth buffer on MCP89 (GeForce 320M) seen on a MacBook Pro Late 2010.

The bug is tracked in https://bugs.freedesktop.org/show_bug.cgi?id=108500Signed-off-by: NTimo Wiren <timo.wiren@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

It'd be nice to have FW loading debug messages to appear for the relevant
subsystem, when enabled.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

      GPL-2.0
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: NKate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Where possible, we want the failsafe link configuration (one which won't
hang the OR during modeset because of not enough bandwidth for the mode)
to also be supported by the sink.

This prevents "link rate unsupported by sink" messages when link training
fails.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Modesetting only, still waiting on ACR/GR firmware from NVIDIA for Turing
graphics/compute bring-up.

Each subsystem was compared with traces, along with various tests to check
that things generally work as they should, and appears compatible enough
with the current TU106 code to enable support.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.

This patch aims to suppress 29 missing-break-in-switch false positives.

Addresses-Coverity-ID: 1456891 ("Missing break in switch")
Addresses-Coverity-ID: 1324063 ("Missing break in switch")
Addresses-Coverity-ID: 1324063 ("Missing break in switch")
Addresses-Coverity-ID: 141432 ("Missing break in switch")
Addresses-Coverity-ID: 141433 ("Missing break in switch")
Addresses-Coverity-ID: 141434 ("Missing break in switch")
Addresses-Coverity-ID: 141435 ("Missing break in switch")
Addresses-Coverity-ID: 141436 ("Missing break in switch")
Reviewed-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com>

This nvclass exposes the replayable fault buffer, which will be used
by SVM to manage GPU page faults.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

MMU will need access to this info.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

MMU will need access to these.

v2. Apply fix from Rhys Kidd to send correct FECS method for STOP_CTXSW.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Future changes will want to add some additional things here, keep them
grouped together.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Makes the code somewhat less magic.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This is already done during golden context creation.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>