This patch adds a watchdog driver for the main hardware watchdog timer
found on MOXA ART SoCs.

The MOXA ART SoC provides one writable timer register, restarting
the hardware once it reaches zero. The register is auto decremented
every APB clock cycle.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Add documentation for the generic OMAP DES crypto modul describing the device
tree bindings.
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

A new compatible property "ti,omap5-sham" is added to the omap-sham driver
recently to support SHA/MD5 for OMAP5,DRA7 and AM43XX. Documenting the
same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add OF document for LM90 in Documentation/devicetree/.

[JD: Add this new file to the LM90 MAINTAINERS entry.]
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Correct the SPI node compatible property items to match example code and
match current DTS usage.
Signed-off-by: NEric Witcher <ewitcher@mindspring.com>
Acked-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

LP8555 is one of the LP855x family devices.

This device needs pre_init_device() and post_init_device() driver
structure.  It's same as LP8557, so the device configuration code is
shared with LP8557.  Backlight outputs are generated from dual DC-DC boost
converters.  It's configurable EPROM settings which are defined in the
platform data.

Driver documentation and device tree bindings are updated.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Updated the number of LDOs and BUCKs as per the user manual.
Fixed trivial typos to improve readability.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Updated supported SoC name for pwm-samsung.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

There was a spelling mistake on TSC/ADC binding where "coordinate" was
spelled as "coordiante".

We can't simply fix the error due to DT being an ABI, the approach taken
was to first use correct spelling and if that fails, fall back to
miss-spelled version.

It's unfortunate that has creeped into the tree.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>

OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
	1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
	1-bit hamming ecc-code using GPMC h/w engine
- OMAP_ECC_HAMMING_CODE_HW_ROMCODE
	1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible
	to ROM code.

This patch combines above multiple ecc-schemes into single implementation:
- OMAP_ECC_HAM1_CODE_HW
	1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible
	ecc-layout.
Signed-off-by: NPekon Gupta <pekon@ti.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

OMAP NAND driver support multiple ECC scheme, which can used in different
flavours, depending on in-build Hardware engines present on SoC.

This patch updates following in DT bindings related to sectionion of ecc-schemes
- ti,elm-id: replaces elm_id (maintains backward compatibility)
- ti,nand-ecc-opts: selection of h/w or s/w implementation of an ecc-scheme
	depends on ti,elm-id. (supported values ham1, bch4, and bch8)
- maintain backward compatibility to deprecated DT bindings (sw, hw, hw-romcode)

Below table shows different flavours of ecc-schemes supported by OMAP devices
+---------------------------------------+---------------+---------------+
| ECC scheme                            |ECC calculation|Error detection|
+---------------------------------------+---------------+---------------+
|OMAP_ECC_HAM1_CODE_HW                  |H/W (GPMC)     |S/W            |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW     |H/W (GPMC)     |S/W            |
|(requires CONFIG_MTD_NAND_ECC_BCH)     |               |               |
+---------------------------------------+---------------+---------------+
|OMAP_ECC_BCH8_CODE_HW                  |H/W (GPMC)     |H/W (ELM)      |
|(requires CONFIG_MTD_NAND_OMAP_BCH &&  |               |               |
| ti,elm-id in DT)                      |               |               |
+---------------------------------------+---------------+---------------+

To optimize footprint of omap2-nand driver, selection of some ECC schemes
also require enabling following Kconfigs, in addition to setting appropriate
DT bindings
- Kconfig:CONFIG_MTD_NAND_ECC_BCH        error detection done in software
- Kconfig:CONFIG_MTD_NAND_OMAP_BCH       error detection done by h/w engine
Signed-off-by: NPekon Gupta <pekon@ti.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Tested-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch adds support for the clocks provided by the Clock Management
Unit of Energy Micro's efm32 Giant Gecko SoCs including device tree
bindings.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Use "panasonic" as the vendor prefix for the Panasonic Corporation.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Chunghwa Picture Tubes Ltd. isn't listed on the stock exchange, so use
the generic "chunghwa" as vendor prefix.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

AU Optronics is listed as AUO on the stock exchange, so use that as the
vendor prefix.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Adds PHYTEC to the list of DT vendor prefixes.
Signed-off-by: NMatt Porter <matt.porter@linaro.org>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Signed-off-by: NSilvio F <silvio.fricke@gmail.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Drivers like clocksource/cadence_ttc and net/macb already use the 'cdns'
prefix for Cadence IP.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Add the AM33xx RNG module's device tree data.
Also add Documentation file describing the data
for the RNG module.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

imx27 pincontrol driver using the imx1 core driver. The DT bindings are
similar to other imx pincontrol drivers.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The standard interrupts property in device tree can only handle
interrupts coming from a single interrupt parent. If a device is wired
to multiple interrupt controllers, then it needs to be attached to a
node with an interrupt-map property to demux the interrupt specifiers
which is confusing. It would be a lot easier if there was a form of the
interrupts property that allows for a separate interrupt phandle for
each interrupt specifier.

This patch does exactly that by creating a new interrupts-extended
property which reuses the phandle+arguments pattern used by GPIOs and
other core bindings.
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
[grant.likely: removed versatile platform hunks into separate patch]
Cc: Rob Herring <rob.herring@calxeda.com>

The GPIO driver for the Abilis Systems TB10x series of SOCs based on ARC700
CPUs. It supports GPIO control and GPIO interrupt generation. This driver
works in conjunction with the TB10x pinctrl driver.
Signed-off-by: NSascha Leuenberger <sascha.leuenberger@abilis.com>
Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch moves the handling of the chip's enable pin from the board
code into the driver. It also updates all board-code files using the
driver to incorporate this change.

This is needed for device tree support of the enable pin.
Signed-off-by: NSebastian Reichel <sre@debian.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NBryan Wu <cooloney@gmail.com>

Support for loading the Renesas HSPI driver via devicetree.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Add device tree support to tpa6130a2 driver and document the
bindings.
Signed-off-by: NSebastian Reichel <sre@debian.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

Device tree support for Davinci Machine driver

When the board boots with device tree, the driver will receive card,
codec, dai interface details (like the card name, DAPM routing map,
phandle for the audio components described in the dts file, codec mclk
speed). The card will be set up based on this information. Since the
routing is provided via DT we can mark the card fully routed so core
can take care of disconnecting the unused pins.
Signed-off-by: NHebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: NDarren Etheridge <detheridge@ti.com>
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Remove last reference to num-serializer in davinci-mcasp devicetree
binding document.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The ams AS3722 is a compact system PMU suitable for mobile phones,
tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
controller, 11 LDOs, RTC, automatic battery, temperature and
over-current monitoring, 8 GPIOs, ADC and a watchdog.

Add MFD core driver for the AS3722 to support core functionality.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NFlorian Lobmaier <florian.lobmaier@ams.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The serial-dir array gives this information so there is no need to have the
num-serializer property in DT description.
Just ignore the property in the driver the DTS files can be updated
separately without regression.
Update the documentation at the same time for davinci-mcasp
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Makes interrupts property optional as the interrupts are not currently
used by the driver and adds interrupt-names property to name listed
interrupts. Currently know interrupt names are "tx" and "rx".

- Improve tdm-slots propery description

- Improve op-mode property description

- Add pinctrl-names and pinctrl-0 properties

- Remove #address-cells and #size-cells as they are not needed.

- Bracket named interrupts property tuples for uniformity.

- Add missing "for" to serial-dir prop in DT bindings doc.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The Armada 370/XP SoCs have a Core Divider clock providing
several clocks. For now, only the NAND clock is supported.
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

An efm32 features 4 16-bit timers with a 10-bit prescaler. This driver
provides clocksource and clock event device using one timer instance
each.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This enables setting a default trigger on an LP55xx channel,
either from platform data or device tree. This mechanism is
identical to the mechanism for GPIO LEDs and references the
common LEDs device tree bindings.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NMilo Kim <milo.kim@ti.com>
Acked-by: NMilo Kim <milo.kim@ti.com>
Signed-off-by: NBryan Wu <cooloney@gmail.com>

Change the model omap2-mcasp-audio in compatible property to
am33xx-mcasp-audio as omap2 does not have mcasp.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

Extract DMA channels directly from DT as they can not be found from
platform resources anymore. This is a work-around until davinci audio
driver is updated to use dmaengine.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

This patch adds a separate register location for data port registers to
mcasp DT bindings. On am33xx SoCs the McASP registers are mapped
trough L4 interconnect, but data port registers are also mapped trough
L3 bus to a different memory location.
Signed-off-by: NHebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: NDarren Etheridge <detheridge@ti.com>
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>

The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources.  This patch adds a mux and a gate for
both of these clocks.
Signed-off-by: NSean Cross <xobs@kosagi.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.
Signed-off-by: NNicolin Chen <b42378@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.

Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

This patch adds support for device tree for the CS42L73 CODEC
Signed-off-by: NBrian Austin <brian.austin@cirrus.com>
Signed-off-by: NMark Brown <broonie@linaro.org>