This implements basic sparsemem support for SH. Presently this only
uses static sparsemem, and we still permit explicit selection of
flatmem. Those boards that want sparsemem can select it as usual.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that select no longer works for selecting the "closest" CPU,
we have to explicitly reference the precise sub-type in the few
places where it actually matters (presently only setup code and
some legacy sh-sci cruft).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This was a big mess, rework the logic a bit so that we constrain
to a particular subtype and figure out the board support based
on that. This makes building subtype specific kernels supporting
multiple boards possible again.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Most SH platforms aren't going to need more than a single active
region, ones that need more can pad this out as necessary.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This moves SH over to the generic quicklists. As per x86_64,
we have special mappings for the PGDs, so these go on their
own list..
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This fixes up SH7705 CPU support and the SE7705 board
for some of the recent changes.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This reworks some of the node 0 bootmem initialization in
preparation for discontigmem and sparsemem support.

ARCH_POPULATES_NODE_MAP is switched to as a result of this.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Support the SH7712 (SH3-DSP) Solution Engine reference board.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add SH7760 IPR IRQ data; makes 2.6.20-rc bootable again.
Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.

With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.

And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This fixes up shmin (and SH7706/SH7708) IPR support for some of the
recent API changes.
Signed-off-by: NTakashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds CPU support for the SH7722.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.

 - adds an ipr_idx to the ipr_data and uses a function in the subtype
   code to calculate the address of the IPR registers

 - adds a function to enable individual interrupt mode for externals
   in the subtype code and calls that from the titan board code
   instead of doing it directly.

 - I changed the shift in the ipr_data to be the actual # of bits to
   shift, instead of the numnber / 4 - made it easier to match with
   the manual.
Signed-off-by: NJamie Lenehan <lenehan@twibble.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds some preliminary support for the SH-X2 MMU, used by
newer SH-4A parts (particularly SH7785).

This MMU implements a 'compat' mode with SH-X MMUs and an
'extended' mode for SH-X2 extended features. Extended features
include additional page sizes (8kB, 4MB, 64MB), as well as the
addition of page execute permissions.

The extended mode attributes are placed in a second data array,
which requires us to switch to 64-bit PTEs when in X2 mode.

With the addition of the exec perms, we also overhaul the mmap
prots somewhat, now that it's possible to handle them more
intelligently.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Simple 7785 placeholders to start hooking up other bits of code.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements initial support for the SH7206 (SH-2A) and SH7619
(SH-2) MMU-less CPUs.
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements initial support for the vsyscall page on SH.
At the moment we leave it configurable due to having nommu
to support from the same code base. We hook it up for the
signal trampoline return at present, with more to be added
later, once uClibc catches up.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for the aforementioned CPU subtypes, and cleans
up some build issues encountered as a result.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A few more outstanding nommu fixups..
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

nommu needs to be able to shift PAGE_OFFSET, so we switch it to a
non-user-visible CONFIG_PAGE_OFFSET and use that in the few places
where it matters.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

SE73180 can use the generic support, we just need to
wire up the IRQ demuxing.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently the CPU subtype options are cluttering up arch/sh/Kconfig somewhat.

Given that, this moves all of that in to its own arch/sh/mm/Kconfig.  Things
like cache configuration are also moved to this new location.

This also adds support for strict CPU tuning on newer cores, which requires
the addition of as-option.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>