1. 23 4月, 2016 1 次提交
    • S
      perf/x86/intel/rapl: Support Skylake RAPL domains · dcee75b3
      Srinivas Pandruvada 提交于
      Add Skylake client support for RAPL domains. In addition to RAPL domains
      in Broadwell clients, it has support for platform domain (aka PSys). The
      PSys domain controls the entire SoC instead of just a CPU package. Unlike
      package domain, PSys support requires more than just processor level
      implementation. The other parts in the system need additional HW level
      signaling, which OEMs need to support. When not supported, the energy
      counter register in PSys domain returns 0.
      
      Also corrected error in comment for GPU counter, which previously was
      DRAM counter.
      
      Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com
      [ Cnverted to model_match stuff. ]
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: bp@alien8.de
      Cc: hpa@zytor.com
      Cc: jacob.jun.pan@linux.intel.com
      Cc: rjw@rjwysocki.net
      Link: http://lkml.kernel.org/r/1460930581-29748-2-git-send-email-srinivas.pandruvada@linux.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@kernel.org>
      dcee75b3
  2. 08 4月, 2016 1 次提交
  3. 31 3月, 2016 2 次提交
    • H
      perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter · aaf24884
      Huang Rui 提交于
      AMD Zeppelin (Family 17h, Model 00h) introduces an instructions
      retired performance counter which is indicated by
      CPUID.8000_0008H:EBX[1]. A dedicated Instructions Retired MSR register
      (MSR 0xC000_000E9) increments once for every instruction retired.
      Signed-off-by: NHuang Rui <ray.huang@amd.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Borislav Petkov <bp@suse.de>
      Cc: Fengguang Wu <fengguang.wu@intel.com>
      Cc: Jacob Shin <jacob.w.shin@gmail.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Kan Liang <kan.liang@intel.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Robert Richter <rric@kernel.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Link: http://lkml.kernel.org/r/1454056197-5893-3-git-send-email-ray.huang@amd.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      aaf24884
    • H
      perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support · 8a224261
      Huang Rui 提交于
      AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter
      which is indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100
      MHz rate in all P-states, and C states, S0, or S1. The frequency is
      about 100MHz. This counter will be used to calculate processor power
      and other parts. So add an interface into the MSR PMU to get the PTSC
      counter value.
      Signed-off-by: NHuang Rui <ray.huang@amd.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Borislav Petkov <bp@suse.de>
      Cc: Fengguang Wu <fengguang.wu@intel.com>
      Cc: Jacob Shin <jacob.w.shin@gmail.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Kan Liang <kan.liang@intel.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Robert Richter <rric@kernel.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Link: http://lkml.kernel.org/r/1454056197-5893-2-git-send-email-ray.huang@amd.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      8a224261
  4. 29 3月, 2016 1 次提交
  5. 08 3月, 2016 1 次提交
  6. 17 2月, 2016 2 次提交
  7. 01 2月, 2016 1 次提交
  8. 24 11月, 2015 1 次提交
  9. 14 11月, 2015 1 次提交
  10. 15 10月, 2015 1 次提交
  11. 21 9月, 2015 1 次提交
  12. 18 9月, 2015 1 次提交
  13. 04 8月, 2015 2 次提交
  14. 07 6月, 2015 2 次提交
  15. 28 5月, 2015 1 次提交
  16. 19 4月, 2015 1 次提交
  17. 14 4月, 2015 1 次提交
    • L
      x86 msr-index: define MSR_TURBO_RATIO_LIMIT,1,2 · c4d30668
      Len Brown 提交于
      MSR_TURBO_RATIO_LIMIT has grown into a set of three registers.
      Add the documented names for them, in preparation
      for deleting the previous ad-hoc names:
      
      +#define MSR_TURBO_RATIO_LIMIT          0x000001ad
      +#define MSR_TURBO_RATIO_LIMIT1         0x000001ae
      +#define MSR_TURBO_RATIO_LIMIT2         0x000001af
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Cc: x86@kernel.org
      c4d30668
  18. 02 4月, 2015 1 次提交
    • A
      perf/x86/intel/pt: Add Intel PT PMU driver · 52ca9ced
      Alexander Shishkin 提交于
      Add support for Intel Processor Trace (PT) to kernel's perf events.
      PT is an extension of Intel Architecture that collects information about
      software execuction such as control flow, execution modes and timings and
      formats it into highly compressed binary packets. Even being compressed,
      these packets are generated at hundreds of megabytes per second per core,
      which makes it impractical to decode them on the fly in the kernel.
      
      This driver exports trace data by through AUX space in the perf ring
      buffer, which is zero-copy mapped into userspace for faster data retrieval.
      Signed-off-by: NAlexander Shishkin <alexander.shishkin@linux.intel.com>
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Kaixu Xia <kaixu.xia@linaro.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Robert Richter <rric@kernel.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: acme@infradead.org
      Cc: adrian.hunter@intel.com
      Cc: kan.liang@intel.com
      Cc: markus.t.metzger@intel.com
      Cc: mathieu.poirier@linaro.org
      Link: http://lkml.kernel.org/r/1422614392-114498-1-git-send-email-alexander.shishkin@linux.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      52ca9ced
  19. 10 2月, 2015 1 次提交
    • L
      tools/power turbostat: decode MSR_*_PERF_LIMIT_REASONS · 3a9a941d
      Len Brown 提交于
      The Processor generation code-named Haswell
      added MSR_{CORE | GFX | RING}_PERF_LIMIT_REASONS
      to explain when and how the processor limits frequency.
      
      turbostat -v
      will now decode these bits.
      
      Each MSR has an "Active" set of bits which describe
      current conditions, and a "Logged" set of bits,
      which describe what has happened since last cleared.
      
      Turbostat currently doesn't clear the log bits.
      Signed-off-by: NLen Brown <len.brown@intel.com>
      3a9a941d
  20. 09 1月, 2015 1 次提交
    • E
      KVM: nVMX: Improve nested msr switch checking · e9ac033e
      Eugene Korenevsky 提交于
      This patch improve checks required by Intel Software Developer Manual.
       - SMM MSRs are not allowed.
       - microcode MSRs are not allowed.
       - check x2apic MSRs only when LAPIC is in x2apic mode.
       - MSR switch areas must be aligned to 16 bytes.
       - address of first and last byte in MSR switch areas should not set any bits
         beyond the processor's physical-address width.
      
      Also it adds warning messages on failures during MSR switch. These messages
      are useful for people who debug their VMMs in nVMX.
      Signed-off-by: NEugene Korenevsky <ekorenevsky@gmail.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e9ac033e
  21. 21 12月, 2014 1 次提交
  22. 03 12月, 2014 1 次提交
  23. 12 11月, 2014 2 次提交
  24. 16 8月, 2014 1 次提交
  25. 19 6月, 2014 1 次提交
  26. 30 5月, 2014 1 次提交
    • F
      x86/xsaves: Detect xsaves/xrstors feature · 6229ad27
      Fenghua Yu 提交于
      Detect the xsaveopt, xsavec, xgetbv, and xsaves features in processor extended
      state enumberation sub-leaf (eax=0x0d, ecx=1):
      Bit 00: XSAVEOPT is available
      Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set
      Bit 02: Supports XGETBV with ECX = 1 if set
      Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set
      
      The above features are defined in the new word 10 in cpu features.
      
      The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies
      the state components that software has enabled xsaves and xrstors to manage.
      If the bit corresponding to a state component is clear in XCR0 | IA32_XSS,
      xsaves and xrstors will not operate on that state component, regardless of
      the value of the instruction mask.
      Signed-off-by: NFenghua Yu <fenghua.yu@intel.com>
      Link: http://lkml.kernel.org/r/1401387164-43416-3-git-send-email-fenghua.yu@intel.comSigned-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      6229ad27
  27. 09 5月, 2014 1 次提交
  28. 14 3月, 2014 2 次提交
  29. 24 2月, 2014 1 次提交
  30. 17 1月, 2014 1 次提交
  31. 15 1月, 2014 1 次提交
  32. 13 11月, 2013 1 次提交
    • L
      tools / power turbostat: Support Silvermont · 144b44b1
      Len Brown 提交于
      Support the next generation Intel Atom processor
      mirco-architecture, formerly called Silvermont.
      
      The server version, formerly called "Avoton",
      is named the "Intel(R) Atom(TM) Processor C2000 Product Family".
      
      The client version, formerly called "Bay Trail",
      is named the "Intel Atom Processor Z3000 Series",
      as well as various "Intel Pentium Processor"
      and "Intel Celeron Processor" brands, depending
      on form-factor.
      
      Silvermont has a set of MSRs not far off from NHM,
      but the RAPL register set is a sub-set of those previously supported.
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      144b44b1
  33. 11 10月, 2013 1 次提交
  34. 26 6月, 2013 1 次提交