- 27 8月, 2019 1 次提交
-
-
由 YueHaibing 提交于
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28: error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control? dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; ^~~~~~~~~~~~~~~~~~~~ dcn20_dpp_pg_control Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this. Reported-by: NHulk Robot <hulkci@huawei.com> Fixes: 8a31820b ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NYueHaibing <yuehaibing@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 24 8月, 2019 9 次提交
-
-
由 Jun Lei 提交于
[why] Previous workaround to prevent a vsync flip to be converted to immediate flip is no longer needed, and is risky because there are cases where it can result in infinite loop. [how] Remove wait loop (which is potentially infinite) before locking pipe Signed-off-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Bayan Zabihiyan 提交于
[Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by: NBayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
dcn20 requires special casing for odm. This change treats odm as alternative to mpc tree on dcn20. This is planned to be fixed in a future refactor Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Zi Yu Liao 提交于
[why] With visual confirm enabled, displays where ODM combine is enabled has a test pattern stuck on the right half of the display even though the display is unblanked. [how] Add a condition to not show the colour ramp test pattern when the display is unblanked. Signed-off-by: NZi Yu Liao <ziyu.liao@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jaehyun Chung 提交于
[How] Allocate memory for default page and program memory block addr into default page addr register. Signed-off-by: NJaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
A previous odm change broke stream enable by always setting n_multiply as if odm was on. This fixes the check for odm by making sure opp count is >1 rather than not 0. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Zi Yu Liao 提交于
[why] With Scatter Gather enabled, HUBP underflows during MPO enabled video playback. hubp_init has a register write that fixes this problem, but the register is cleared when HUBP gets power gated. [how] Make a call to hubp_init during enable_plane, so that the fix can be applied after HUBP powers back on again. Signed-off-by: NZi Yu Liao <ziyu.liao@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Su Sung Chung 提交于
[Why] Disable_audio_stream gets enum option as a paramenter which will decide if we free acquired resources or not. However checks for the option is guarded by the other condition which check if audio stream is getting diabled more than once. With both conditions combined, if we attempt to disable audio stream twice in a row, first with keep and second with free as an option, we will never free any resources, which will make system think there is audio endpoint connected even after we plug out the device [How] Get rid of option as parameter to disable_audio_stream and move the part of the code that free acquired resources to outside where to keep or to free resources is actually determined Signed-off-by: NSu Sung Chung <Su.Chung@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
Currently odm is handled using top_bottom pipe by special casing the differing opps to differentiate from mpc combine. Since top/bottom pipe list was made to track mpc muxing this creates difficulties in adding a 4 pipe odm case support. Rather than continue using mpc combine list, this change reworks odm to use it's own linked list to keep track of odm combine pipes. This also opens up options for using mpo with odm, if a practical use case is ever found. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 23 8月, 2019 1 次提交
-
-
由 David Francis 提交于
This reverts commit 6c5be4ac. This commit was accidentally promoted twice Signed-off-by: NDavid Francis <David.Francis@amd.com> Reviewed-by: NRoman Li <Roman.Li@amd.com> Reviewed-by: NHarry Wentland <harry.wentland@amd.com> Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 15 8月, 2019 7 次提交
-
-
由 Charlene Liu 提交于
Enable dcn_mem_pwr as golden setting updates Signed-off-by: NCharlene Liu <charlene.liu@amd.com> Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Charlene Liu 提交于
[Description] OGAM_MEM_PWR could stay in light up when driver woke up to update gamma. either disable MEM_LOW power feature or set to OGAM_bypass could make artificial color distortion goes away. Easy reproduce after LOW_MEM Power feature enables and resume from S3. Signed-off-by: NCharlene Liu <charlene.liu@amd.com> Reviewed-by: NJulian Parkin <jparkin@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
Current optc odm interface only accepts 2 opps, we need to expand this to allow 4 to 1 odm combine. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Martin Leung 提交于
[Why] For seamless boot the init_hw sequence must be split into actual hardware vs pipes, in order to defer pipe initialization to set mode and skip of pipe-destructive sequences [How] made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit deleted dcn20 specific versions. This is part 1 of a 2 partimplementation of seamless boot Signed-off-by: NMartin Leung <martin.leung@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jun Lei 提交于
[why] When planes are enabled, they must be enabled using VSYNC update (not immediate). However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address only. This operation would normally be okay, but if the locking for immediate flip happens to occur before the VUPDATE associated with the initial plane enablement, it will cause HW to hang. [how] HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane. Signed-off-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
Currently every time DC wants to access firmware info we make a call into VBIOS. This makes no sense as there is nothing that can change runtime inside fw info and can cause issues when calling unstable bios during bringup. This change eliminate this behavior by only calling bios once for fw info and keeping it stored as part of dc_bios. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NChris Park <Chris.Park@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Wenjing Liu 提交于
[why] drr is still enabled after driver is unloaded causing black screen [how] disable drr during pipe reset. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 31 7月, 2019 1 次提交
-
-
由 Alex Deucher 提交于
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard. Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 19 7月, 2019 18 次提交
-
-
由 Nicholas Kazlauskas 提交于
[Why] DC configures the GSL group for the pipe when pipe_split is enabled and we're switching flip types (buffered <-> immediate flip) on DCN2. In order to record what GSL group the pipe is using DC stores it in the pipe's stream_res. DM is not aware of this internal grouping, nor is DC resource. So when DM creates a dc_state context and passes it to DC the current GSL group is lost - DM never knew about it in the first place. After 3 immediate flips we run out of GSL groups and we're no longer able to correctly perform *any* flip for multi-pipe scenarios. [How] The gsl_group needs to be copied to the new context. DM has no insight into GSL grouping and could even potentially create a brand new context without referencing current hardware state. So this makes the most sense to have happen in DC. There are two places where DC can apply a new context: - dc_commit_state - dc_commit_updates_for_stream But what's shared between both of these is apply_ctx_for_surface. This logic only matters for DCN2, so it can be placed in dcn20_apply_ctx_for_surface. Before doing any locking (where the GSL group is setup) we can copy over the GSL groups before committing the new context. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NHersen Wu <hersen.wu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Tony Cheng 提交于
Signed-off-by: NTony Cheng <tony.cheng@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jun Lei 提交于
[why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality. Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC functionality, but not all latencies have to be supported. Existing code supports a "full p state" which allows memory clock to change, but is hard for DCN to support (as it requires very large buffers). New code will now fall back to a "dummy p state" support when "full p state" cannot be support. This easy p state support should always be allowed. [how] Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure that fallback will always work. Signed-off-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Julian Parkin 提交于
[Why] Code to enable DCN20 dynamic metadata feature is duplicated in two places and was added to DCE110 enable stream. [How] Create DCN20 specific enable stream function for clarity, and add a hardware sequencer function to program dynamic metadata to avoid the duplicate code. Signed-off-by: NJulian Parkin <julian.parkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Ilya Bakoulin 提交于
[Why] Alpha could be improperly applied (only affecting half the frame) for some source pixel formats. [How] Change how alpha is enabled in MPC/DPP LB and change the bottom plane blend mode in MPC. Signed-off-by: NIlya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Vitaly Prosyak 提交于
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NGary Kattan <Gary.Kattan@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alvin Lee 提交于
[why] In pipe split issue occurs when we program immediate flip while vsync flip is pending [how] Don't program immediate flip until flip is no longer pending Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NJaehyun Chung <Jaehyun.Chung@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Nikola Cornij 提交于
[why] DSC should be powered-on only on as-needed basis, i.e. if the mode requires it [how] Loop over all the DSCs at driver init time and power-gate each Signed-off-by: NNikola Cornij <nikola.cornij@amd.com> Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
This change adds EMP packet programming for enabling dsc with hdmi. The packets are structured according to VESA HDMI 2.1x r2 spec, section 10.10.2.2. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Wenjing Liu 提交于
[why] The current code will not wait for the entire frame after global unlock. This causes dsc dynamic target bpp update corruption when there is a surface update immediately happens after this. [how] Wait for the entire whole frame after unlock before continuing the rest of stream and surface update. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Charlene Liu 提交于
There are shared regs and code across DCN generations. Pull them out into a shared common location. Also, expose some dcn20 init functions. Signed-off-by: NCharlene Liu <charlene.liu@amd.com> Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jun Lei 提交于
[why] Currently logical values are swapped in HW, causing system aperture to be undefined, so VA and PA cannot co-exist [how] program values correctly Signed-off-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
A regression caused dsc to never get disabled in certain situations. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Alvin Lee 提交于
[why] In pipe split issue occurs when we program immediate flip while vsync flip is pending [how] Don't program immediate flip until flip is no longer pending Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NJaehyun Chung <Jaehyun.Chung@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Wenjing Liu 提交于
[why] The current code will not wait for the entire frame after global unlock. This causes dsc dynamic target bpp update corruption when there is a surface update immediately happens after this. [how] Wait for the entire whole frame after unlock before continuing the rest of stream and surface update. Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Jun Lei 提交于
[why] Currently logical values are swapped in HW, causing system aperture to be undefined, so VA and PA cannot co-exist [how] program values correctly Signed-off-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
A regression caused dsc to never get disabled in certain situations. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 hersen wu 提交于
[WHY] dc sw clock implementation of navi10 and raven are not exact the same. dcccg, dchub reference clock initialization is done after dc calls vbios dispcontroller_init table. for raven family, before dispcontroller_init is called by dc, the ref clk values are referred by sw clock implementation and program asic register using wrong values. this causes dchub pstate error. This need provide valid ref clk values. for navi10, since dispcontroller_init is not called, dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will hit aeert. this need remove hubbub2_get_dchub_ref_freq from this location and move to dcn20_init_hw. [HOW] for all asic, initialize dccg, dchub ref clk with data from vbios firmware table by default. for raven asic family, use these data from vbios, for asic which support sw dccg component, like navi10, read ref clk by sw dccg functions and update the ref clk. Signed-off-by: Nhersen wu <hersenxs.wu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NLeo Li <sunpeng.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 09 7月, 2019 1 次提交
-
-
由 Arnd Bergmann 提交于
Without this header, we get a compiler error in some configurations: .../dc/dcn20/dcn20_hwseq.c: In function 'dcn20_hwss_wait_for_blank_complete': .../dc/dcn20/dcn20_hwseq.c:1493:3: error: implicit declaration of function 'udelay' [-Werror=implicit-function-declaration] Note: the use of udelay itself may be problematic, as can occupy the CPU for 200ms in a busy-loop here. Fixes: 7ed4e635 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
- 22 6月, 2019 2 次提交
-
-
由 Thomas Lim 提交于
[Why] For debugging underflow issues it can be useful to have asserts when the underflow initially occurs. [How] Read the underflow status registers after actions that have a high risk of causing underflow and assert that no underflow occurred. If underflow occurred, clear the bit. Signed-off-by: NThomas Lim <Thomas.Lim@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-
由 Dmytro Laktyushkin 提交于
Currently vmid is decided internally inside dc. With the introduction of new asics we are required to coordinate vmid use with external components. This change converts vmid logic to a DAL module allowing vmid to be passed in as a parameter to DC. Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
-