Aside of the usual motivation for constification,  this function has a
history of being abused a hook for interrupt and other fixups so I turned
this function const ages ago in the MIPS code but it should be done
treewide.

Due to function pointer passing in varous places a few other functions
had to be constified as well.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
To: Anton Vorontsov <avorontsov@mvista.com>
To: Chris Metcalf <cmetcalf@tilera.com>
To: Colin Cross <ccross@android.com>
Acked-by: N"David S. Miller" <davem@davemloft.net>
To: Eric Miao <eric.y.miao@gmail.com>
To: Erik Gilling <konkers@android.com>
Acked-by: NGuan Xuetao <gxt@mprc.pku.edu.cn>
To: "H. Peter Anvin" <hpa@zytor.com>
To: Imre Kaloz <kaloz@openwrt.org>
To: Ingo Molnar <mingo@redhat.com>
To: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
To: Krzysztof Halasa <khc@pm.waw.pl>
To: Lennert Buytenhek <kernel@wantstofly.org>
To: Matt Turner <mattst88@gmail.com>
To: Nicolas Pitre <nico@fluxnic.net>
To: Olof Johansson <olof@lixom.net>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
To: Richard Henderson <rth@twiddle.net>
To: Russell King <linux@arm.linux.org.uk>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-pci@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: sparclinux@vger.kernel.org
Cc: x86@kernel.org
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>

For the SMP case we run in to a lockup without a full synchronization
prior to continuing with the boot.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

SH-X3 controllers all have pretty dire delays needed for PHY wakeup, so
we attempt to mitigate the damage by bringing them up asynchronously,
simply using the synchronization points for persistent bridge to channel
numbering.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds a pci setting revision for landisk.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This takes a bit of a sledgehammer to the machvec I/O routines. The
iomem case requires no special casing and so can just be dropped
outright. This only leaves the ioport casing for PCI and SuperIO
mangling. With the SuperIO case going through the standard ioport
mapping, it's possible to replace everything with generic routines.

With this done the standard I/O routines are tidied up and NO_IOPORT
now gets default-enabled for the vast majority of boards.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Instead of hand-rolling our own, just use the generic ones instead.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The SDK7786 FPGA has secondary control over the PCIe clocks, specifically
relating to the slots and oscillator. This ties the FPGA clocks in to the
clock framework and balances the refcounting similar to how the primary
on-chip clocks are managed. While the on-chip clocks are per-port, the
FPGA clock enable/disable is global for the entire block.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

SDK7786 supports connecting either slot3 or 4 to the same PCIe port by
way of FPGA muxing. By default the vertical slot 3 on the baseboard is
enabled, so this adds in a command line option for forcibly enabling the
slot 4 edge connector.

If nothing has been specified on the command line, we fall back to
reading the resistor values for card presence to figure out where to
route the port to.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This copies the pci_config_lock idea from x86 over, allowing us to kill
off a couple of existing private locks. At the same time, these need to
be converted to raw spinlocks for -rt kernels, so we make that change at
the same time. This should make it easier for future parts to get the
locking right instead of inevitable ending up with lock type mismatches.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This gets each port handling its MSTP bit, as well as moving the PHY
clock management in to the clock framework.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Some of the existing code is flipping between __raw_xxx() and
pci_{read,write}_reg(). As the latter are just wrappers for the former,
flip over to using them consistently.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Presently we error out if a link is disabled and simply drop the port
registration outright. This follows the PPC changes and simply reports on
the link state on boot, leaving the port registered, in order to more
easily deal with hotplug on future parts.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

These settings are properly propagated by the hardware already, so
there's no need to bother with them manually.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The SH7786 PCIe is presently unable to enumerate itself in root complex
mode, and has no visibility through either type 0 or type 1 accesses,
despite having a mostly sensible extended config space for each port.
Attempts to generate type 0 or type 1 config cycles result in completer
aborts, so we're ultimately forced to use SuperHyway transactions
instead.

As each port has a single port <-> device mapping that resolves for any
PCI_SLOT definition, we simply hijack devfn 0 for the SuperHyway
transaction and bump up the devfn limit.

With enumeration of the root complex now possible, we also need to insert
an early fixup to hide the BARs from the kernel. With all of that done,
it's now possible to use the pcieport services with all of the PCIe
ports, which is the first step to power management support.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Previously these IDs were only used by one driver, so there was not much
need for having them generically defined. Now that this will no longer
hold true, move them over.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The spec suggests waiting up to 500ms for the PHY to settle before
testing link state, but practice shows that 100ms is sufficient (this is
the delay value we also use on the other SH-4A PCI controllers, too).
This makes device detection much more reliable, although in the future it
should be a bit faster to simply serialize with a TLP IRQ.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

After configuration accesses have been completed deassert the
configuration access enable cleanly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that the resource assignment issues are resolved, we can finally wire
up the small third memory window -- in the future we may reclaim this for
MSI.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

An IORESOURCE_IO was missing here, which meant that we weren't properly
establishing the I/O window for this particular slot. With this
corrected, cards with I/O BARs have them actually assigned and
accessible.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Certain memory windows are only available for 32-bit space, so skip over
these in 29-bit mode. This will severely restrict the amount of memory
that can be mapped, but since a boot loader bug makes booting in 29-bit
mode close to impossible anyways, everything is ok.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This bumps up the low address to match the physical memory windows for
SHway<->PCIe transfers. The previous implementation was banking on a 1:1
virt<->phys SHway mapping, which doesn't apply here.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This attempts a more complete port reset, building on top of the existing
approach.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NMatt Fleming <matt@console-pimps.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

SH7786 PCIe has 1 slot per port, but no specific restriction on function.
Relax the devfn restriction and look to the slot number instead when
configured as a root complex.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This brings the clocking and register setting in line with the somewhat
factually ambiguous specification.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This enables support for type 1 config space accesses on the SH7786
PCI controller. At the same time, add in some extra sanity checks for
controller asserted errors.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This typo seems to have been copy and pasted in the PCI initialization
code. Replace 'intialization' with 'initialization'.
Signed-off-by: NMatt Fleming <matt@console-pimps.org>

pcibios_fixup_device_resources() presently skips over resources flagged
with IORESOURCE_PCI_FIXED, which is a remnant of the old PCI-auto code.
The only user for this at present is the Dreamast GAPSPCI code which
can't tolerate any adjustments to the BARs, but a combination of the
IORESOURCE_PCI_FIXED and zeroed out hose offsets does the right thing for
this case already, so we simply kill off the special casing.
Reported-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch updates the sh7751 pci code to handle io ports
correctly. The code is based on the sh7788x implementation.

Tested on a R2D-1 board with CONFIG_8139TOO_PIO=y.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h

percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

Now that we return the new resource start position, there is no
need to update "struct resource" inside the align function.
Therefore, mark the struct resource as const.

Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: NDominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

As suggested by Linus, align functions should return the start
of a resource, not void. An update of "res->start" is no longer
necessary.

Cc: Bjorn Helgaas <bjorn.helgaas@hp.com>
Cc: Yinghai Lu <yhlu.kernel@gmail.com>
Signed-off-by: NDominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This reworks some of the SH7786 PCIe initialization code to dynamically
setup and size the various resource windows, as opposed to the original
code that simply wired in a couple of them statically.

At the same time, we tidy up the initialization code a bit, kill off some
read-only register twiddling that was gleaned from the bus analyzer, and
also propagate the physical slot/channel mapping.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds in some of the missing memory resources for channels 1/2 and
gets the code building again for the recent changes.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for handling early PERR/SERR triggering in between
controller registration and the initial bus scan. Buggy cards end up
asserting these as soon as the M66EN scan is undertaken, resulting in
an early crash.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The SH7780 PCI controller supports 3 different ranges of PCI memory in
addition to its PCI I/O window. In the case of 29-bit mode, only 2 memory
windows are supported, while in 32-bit mode all 3 are visible. This
attempts to make the resource handling completely dynamic and to permit
platforms to map in as many apertures as they can handle.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>