Add LPSC id for DA850's MMCSD1 peripheral.
Signed-off-by: NJuha Kuikka <juha.kuikka@elektrobit.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode
specific pin lists, while what pin group is used is a function of how the board
is wired.  Copy the pin lists to board-da850-evm.c, renaming them accordingly,
and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing
the CPGMAC module as a whole...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board
specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c,
renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the
two lists in da850.c into one, representing the EMIF 2.5 module as a whole,
just like we have it in da830.c...

While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as
this function is called from non '__init' code...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF
timing to remain valid even as the PLL0 output is changed by cpufreq
driver to save power.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Not all the channels and slots available on the DM646x EVM
are used by the devices on the EVM. These resources can be
used by the DSP to speed up codec operations.

This patch reserves these channels for the DSP.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The drivers on da8xx/omapl EVMs do not utilize all the channels
and slots provided by EDMA. Some of these are better utilitzed by
the DSP on the SoC for speeding up codec operations.

Reserve these channels/slots for the DSP.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current EDMA driver is not taking care of EDMA channels/slots
which are allocated from other processor, say DSP. If a
channel/slot is allocated from DSP, the existing EDMA driver
can still allocate the same resource on ARM.

This patch enables the user to pass the channel/slots reserved
for DSP as platform data. EDMA driver scans this list during
probe and prepares a bitmap of channel/slots which can be used
on ARM side.

Trying to reserve channels by doing a 'pre-allocate' using
edma_alloc_{slot|channel}() API does not work because

1) The reservation should be done in probe() to avoid race
   with other ARM side driver trying to use EDMA

2) The alloc channel API sets up the access through shadow region
   0 which will be incorrect for DSP usage. It also sets up the
   channel <-> queue number mapping which is not required as DSP
   will likely do its own mapping anyway.

3) (minor) There is no API to allocate channels in bulk.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the EDMA driver to expect the channel
controller (CC) infomation passed on by the platform as a fixed
size (EDMA_MAX_CC) array of pointers to structures.

Doing so helps catch errors of the sort where the resource
structure has information for more channel controllers than
the number channel controller info structures defined.

Such insufficient platform data would lead to illegal memory
accesses.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Currently the EDMA queue to be used by for servicing ASP through
internal RAM is fixed to EDMAQ_0 and that to service internal RAM
from external RAM is fixed to EDMAQ_1.

This may not be the desirable configuration on all platforms. For
example, on DM365, queue 0 has large fifo size and is more suitable
for video transfers. Having audio and video transfers on the same
queue may lead to starvation on audio side.

platform data as defined currently passes a queue number to the driver
but that remains unused inside the driver.

Fix this by defining one queue each for ASP and RAM transfers in the
platform data and using it inside the driver.

Since EDMAQ_0 maps to 0, thats the queue that will be used if
the asp queue number is not initialized. None of the platforms
currently utilize ping-pong transfers through internal RAM so that
functionality remains unchanged too.

This patch has been tested on DM644x and OMAP-L138 EVMs.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Since we no longer support discontigmem, node is always zero, so
remove this argument.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

    i2s_accurate_sck switch can be used to have a better approximate
    sampling frequency.
    The clock is an externally visible bit clock and it is named
    i2s continuous serial clock (I2S_SCK).
    The trade off is between more accurate clock (fast clock)
    and less accurate clock (slow clock).
    The waveform will be not symmetric.
    Probably it is possible to get a better algorithm for calculating
    the divider, trying to keep a slower clock as possible.

    This patch has been developed against the
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm, but using
    uda1345 as external audio codec).
Signed-off-by: NRaffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Acked-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

    When McBSP peripheral gets the clock from an external pin,
    there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
    and MCBSP_CLKS.
    evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
    hardware connection and I use MCBSP_CLKS, so I have added
    this possibility.

    This patch has been developed against the:
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm)
Signed-off-by: NRaffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Acked-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This patch adds support for the tnetv107x gpio controller.

Key differences between davinci and tnetv107x controllers:
 - register map - davinci's controller is organized into banks of 32 gpios,
   tnetv107x has a single space with arrays of registers for in, out,
   direction, etc.
 - davinci's controller has separate set/clear registers for output, tnetv107x
   has a single direct mapped register.

This patch does not yet add gpio irq support on this controller.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

TNETV107X is a Texas Instruments SOC that shares a number of common features
with the Davinci architecture.  Some of the key differences between
traditional Davincis and this new SOC are as follow:

1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
elements of the clock architecture are reused from Davinci (e.g. LPSC), but
the PLL related code is overridden using existing interfaces in "struct clk".

2. The MMR layout on this SOC is substantially different from Davinci.
Consequently, the fixed I/O map is a whole lot more convoluted (more so than
DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
and therefore all mappings have to be through ioremap().
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Added definitions for tnetv107x uart base addresses, and modified base address
selection for kernel decompressor to check for tnetv107x machine type.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adopts a debug uart selection similar to the OMAP model.  During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart.  These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On some platforms like DM355, the number of EDMA parameter slots available
for EDMA_SLOT_ANY usage are few.  In such cases, if MMC/SD uses 16 slots
for each instance of MMC controller, then the number of slots available
for other modules will be very few.

By passing the number of EDMA slots to be used in MMC driver from platform
data, EDMA slots available for other purposes can be controlled.

Most of the platforms will not use this platform data variable.  But on
DM355, as the number of EDMA resources available is limited, the number of
scatter- gather segments used inside the MMC driver can be 8 (passed as
platform data) instead of 16.  On DM355, when the number of scatter-gather
segments was reduced to 8, I saw a performance difference of about
0.25-0.4 Mbytes/sec during write.  Read performance variations were
negligible.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Acked-by: NKevin Hilman <khilman@deeprootsystems.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

More complete AEMIF support for boards.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Added PINMUX configurations for the CLKOUT0 .. CLKOUT2
functions, for boards that want to use these clocks.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Board code may want to use them.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows for a more flexible ioremap() interception based on iotable
contents.

With this patch, the ioremap() interception code can properly translate
addresses only after davinci_soc_info has been initialized.  Consequently,
in soc-specific init functions, davinci_common_init() has to happen before any
ioremap() attempts. The da8xx init sequence has been suitably modified to meet
this restriction.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch implements the following:

 - interrupt initialization uses ioremap() instead of passing a virtual address
   via davinci_soc_info.

 - machine definitions directly point to cp_intc_init() or davinci_irq_init()

 - davinci_intc_type and davinci_intc_base now get initialized in controller
   specific init functions instead of davinci_common_init()

 - minor fix in davinci_irq_init() to use intc_irq_num instead of
   DAVINCI_N_AINTC_IRQ
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the psc and clock control code to use ioremap()ed
registers.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch eliminates IO_ADDRESS() usage for Davinci timer definitions.  The
timer code has correspondingly been modified to ioremap() MMRs instead.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch replaces the jtag id base info in davinci_soc_info with a physical
address which is then ioremap()ed within common code.

This patch (in combination with a similar change for PSC) will allow us to
eliminate the SYSCFG nastiness in DA8xx code.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the gpio_base definition in davinci_soc_info to be a
physical address, which is then ioremap()ed by the gpio initialization
function.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The uart pdata array is already terminated by a zero flag field.

This patch reuses this terminator and eliminates DAVINCI_MAX_NR_UARTS
definition.  This way, future platforms can have different number of uarts
initialized via davinci_serial_init().
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The earlier watchdog reset mechanism had a couple of limitations.  First, it
embedded a reference to "davinci_wdt_device" inside common code.  This
forced all derived platforms (da8xx and tnetv107x) to define such a device.
This also would have caused problems in including multiple socs in a single
build due to symbol redefinition.

With this patch, davinci_watchdog_reset() now takes the platform device as an
argument.  The davinci_soc_info struct has been extended to include a reset
function and a watchdog platform_device.  arch_reset() then uses these
elements to reset the system in a SoC specific fashion.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Pinmux registers are sequential, and do not need to be enumerated out as they
currently are.  This reduces code volume and keeps things simple.

If some future SoC comes up with a discontiguous register map, PINMUX() can
then be expanded with local token pasting.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch eliminates the global gpio_lock, and implements a per-controller
lock instead.  This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows for gpio controllers that deviate from those found on
traditional davinci socs.  davinci_soc_info has an added field to indicate the
soc-specific gpio controller type.  The gpio initialization code then bails
out if necessary.

More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout.  This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.

Other changes:

1. davinci_gpio_regs structure definition moved to gpio.c.  This structure is
no longer common across all davinci socs (davinci_gpio_controller is).

2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.

3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Renamed gpio types to something more sensible:
	struct gpio_controller	--> struct davinci_gpio_regs
	struct davinci_gpio	--> struct davinci_gpio_controller
	gpio2controller()	--> gpio2regs()
	irq2controller()	--> irq2regs()

This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Tested-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The IDE platform device is registered in three different places (2 board files
for DM644x and in dm646x.c for DM646x) while both the IDE base address and the
IDE IRQ are the same for both SoCs -- therefore,  the proper place for the IDE
platform seems to be in devices.c. Merge the IDE platform data and registration
code and create davinci_init_ide() in place of dm646x_init_ide()...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

linux/compiler.h is required for __iomem
linux/types.h is required u32
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Extended the MUX configuration to allow use of GPIO
terminals 64..57.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Currently each DaVinci board file #define's its own version of the EMIFA base
addresses (all named DAVINCI_ASYNC_EMIF_*_BASE), which leads to duplication.
Move these #define's to the SoC specific headers, changing their prefixes from
'DAVINCI' to the 'DM355', 'DM644X', and 'DM646X' since all these base addresses
are SoC specific...

And while at it, rename DM646X_ASYNC_EMIF_DATA_CE0_BASE to
DM646X_ASYNC_EMIF_CS2_SPACE_BASE in order to match the DM646x datasheet.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Added tnetv107x cpu type definitions and cpu identification macros.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

IRQ numbers as defined for tnetv107x cp_intc.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>