Add LPSC id for DA850's MMCSD1 peripheral.
Signed-off-by: NJuha Kuikka <juha.kuikka@elektrobit.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

If irq2ctlr() fails return IRQ_NONE.
Also as it can fail make 'ctlr' signed.

The semantic patch that finds this problem (many false-positive results):
(http://coccinelle.lip6.fr/)

// <smpl>
@ r1 @
identifier f;
@@
int f(...) { ... }

@@
identifier r1.f;
type T;
unsigned T x;
@@

*x = f(...)
 ...
*x > 0
Signed-off-by: NKulikov Vasiliy <segooon@gmail.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode
specific pin lists, while what pin group is used is a function of how the board
is wired.  Copy the pin lists to board-da850-evm.c, renaming them accordingly,
and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing
the CPGMAC module as a whole...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board
specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c,
renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the
two lists in da850.c into one, representing the EMIF 2.5 module as a whole,
just like we have it in da830.c...

While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as
this function is called from non '__init' code...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Tested-by: NBen Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This is a bugfix for the original tnetv107x submission series.  The psc_regs
base array was being discarded post-init, and this was causing a crash during
post-init clock enable/disable.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF
timing to remain valid even as the PLL0 output is changed by cpufreq
driver to save power.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On OMAP-L138 SoC, some of the sysclks need not be at a fixed ratio
to CPU clock and can be kept at a relatively constant rate by
adjusting the PLLDIVn ratio even as cpufreq goes ahead and changes
the CPU clock.

This feature can be used to keep the EMIFA (PLL0 SYSCLK3) clock at a
constant rate so that the EMIF timings need not be re-programmed
whenever the CPU frequency changes.

This patch adds the required suppport to cpufreq driver.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Setting sysclk rate will be useful in cases where the
sysclk is not at a fixed ratio to the PLL output but
can asynchronously be changed.

This support forms the basis of attempt to keep the AEMIF
clock constant on OMAP-L138 even as PLL0 output changes
as ARM clock is changed to save power.

This patch has been tested on OMAP-L138.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch disables internal pulldowns for all MMC/SD1
pins. Presently only MMCSD1_CMD pin's pull down is
disabled, but with this some MMC/SD cards do not get
detected on MMC/SD1 slot of the EVM.

The problem was reproducible with SanDisk 4GB SDHC card.
Reported-by: NStephane Bovagne <s-bovagne@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical
reference manual (TRM) is actually the minimum voltage the frequency
is supported at.

The minimum ('MIN') voltage defined in TRM is meant to take care of
voltage fluctuations and the device should not be run at this voltage
for extended periods of time.

Fix the OPP definitions to define the cvdd_min as the normal voltage
defined in the datasheet.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin
compatible ARM9 microprocessor offering from TI.

The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin
compatible ARM9 microprocessor offering from TI.

More information about these processors available at:
www.ti.com/am1x

Because of their compatibiliy with OMAP-L1x, the kernel
support for OMAP-L1x is fully relevant to AM1x processors.

This patch updates the Kconfig prompt and help text to include
the AM1x part names to help users select configurations required
for these parts easily.

Also, the hardware information that shows up in /proc/cpuinfo
is updated to show applicability of the respective OMAP-L1x EVMs
for AM1x parts.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

In arch/arm/mach-davinci/Kconfig, some of the configuration
items are indented with multiple spaces instead of tabs.

Also, in couple of places, two spaces are used in the middle
of help text where one should do.

This patch fixes both issues.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current cpufreq code does not consider errors that can occur while
changing voltage. Code to increase CPU  frequency goes ahead even in
the case the regulator has failed to increase the voltage. This leads
to hard error since lower voltages cannot support increased frequency.

Prevent this by not increasing frequency in case increasing voltage
is not successful.

Also, do not lower the voltage if changing the cpu frequency has failed
for some reason.

Note that we do not return error on failure to decrease voltage as
that is not a hard error.

Build fix for non-cpufreq kernels by Caglar Akyuz.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Cc: Caglar Akyuz <caglar@bilkon-kontrol.com.tr>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The long list of clocks being disabled on boot is noisy and not needed
for standard boots.   Make this a debug printk instead.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Without this cleanup, sparse checker reports warnings of the type:

  CHECK   arch/arm/mach-davinci/board-da850-evm.c
arch/arm/mach-davinci/board-da850-evm.c:112:22: warning: symbol 'da850_evm_nandflash_partition' was not declared. Should it be static?

The nand flash partitions and regulator supplies are used within
the EVM file and so should have been static

This patch has been boot tested on DA830 and DA850 EVMs.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Not all the channels and slots available on the DM646x EVM
are used by the devices on the EVM. These resources can be
used by the DSP to speed up codec operations.

This patch reserves these channels for the DSP.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The drivers on da8xx/omapl EVMs do not utilize all the channels
and slots provided by EDMA. Some of these are better utilitzed by
the DSP on the SoC for speeding up codec operations.

Reserve these channels/slots for the DSP.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current EDMA driver is not taking care of EDMA channels/slots
which are allocated from other processor, say DSP. If a
channel/slot is allocated from DSP, the existing EDMA driver
can still allocate the same resource on ARM.

This patch enables the user to pass the channel/slots reserved
for DSP as platform data. EDMA driver scans this list during
probe and prepares a bitmap of channel/slots which can be used
on ARM side.

Trying to reserve channels by doing a 'pre-allocate' using
edma_alloc_{slot|channel}() API does not work because

1) The reservation should be done in probe() to avoid race
   with other ARM side driver trying to use EDMA

2) The alloc channel API sets up the access through shadow region
   0 which will be incorrect for DSP usage. It also sets up the
   channel <-> queue number mapping which is not required as DSP
   will likely do its own mapping anyway.

3) (minor) There is no API to allocate channels in bulk.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the EDMA driver to expect the channel
controller (CC) infomation passed on by the platform as a fixed
size (EDMA_MAX_CC) array of pointers to structures.

Doing so helps catch errors of the sort where the resource
structure has information for more channel controllers than
the number channel controller info structures defined.

Such insufficient platform data would lead to illegal memory
accesses.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch helps get rid of the following sparse warnings
of the type:

  CHECK   arch/arm/mach-davinci/da830.c
arch/arm/mach-davinci/da830.c:1026:3: warning: Initializer entry defined twice
arch/arm/mach-davinci/da830.c:1027:3:   also defined here

coming from the irq priorities array init.

Apart from one instance of genuinie repetition, most are are instances
of multiple #defines of the same interrupt number. I have not
removed the multiple definitions from the irq.h file in the hope
that someone might decide to use them as shared interrupts at some
point of time. The priority initialization however needs to be done
only once and hence has been corrected.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The register base address for the second serial port (UART1) was
wrong.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Per the da850/omap-l138 Beta EVM SOM schematic, the DEFDCDC2 and
DEFDCDC3 lines are tied high. This leads to a 3.3V IO and 1.2V CVDD
voltage.

Pass the right platform data to the TPS6507x driver so it can operate
on the DEFDCDC{2,3}_HIGH register to read and change voltage levels.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NLiam Girdwood <lrg@slimlogic.co.uk>

Currently the EDMA queue to be used by for servicing ASP through
internal RAM is fixed to EDMAQ_0 and that to service internal RAM
from external RAM is fixed to EDMAQ_1.

This may not be the desirable configuration on all platforms. For
example, on DM365, queue 0 has large fifo size and is more suitable
for video transfers. Having audio and video transfers on the same
queue may lead to starvation on audio side.

platform data as defined currently passes a queue number to the driver
but that remains unused inside the driver.

Fix this by defining one queue each for ASP and RAM transfers in the
platform data and using it inside the driver.

Since EDMAQ_0 maps to 0, thats the queue that will be used if
the asp queue number is not initialized. None of the platforms
currently utilize ping-pong transfers through internal RAM so that
functionality remains unchanged too.

This patch has been tested on DM644x and OMAP-L138 EVMs.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Since we no longer support discontigmem, node is always zero, so
remove this argument.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

    i2s_accurate_sck switch can be used to have a better approximate
    sampling frequency.
    The clock is an externally visible bit clock and it is named
    i2s continuous serial clock (I2S_SCK).
    The trade off is between more accurate clock (fast clock)
    and less accurate clock (slow clock).
    The waveform will be not symmetric.
    Probably it is possible to get a better algorithm for calculating
    the divider, trying to keep a slower clock as possible.

    This patch has been developed against the
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm, but using
    uda1345 as external audio codec).
Signed-off-by: NRaffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Acked-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

    When McBSP peripheral gets the clock from an external pin,
    there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
    and MCBSP_CLKS.
    evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
    hardware connection and I use MCBSP_CLKS, so I have added
    this possibility.

    This patch has been developed against the:
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm)
Signed-off-by: NRaffaele Recalcati <raffaele.recalcati@bticino.it>
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Acked-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Added support for tnetv107x evaluation module.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds support for the tnetv107x gpio controller.

Key differences between davinci and tnetv107x controllers:
 - register map - davinci's controller is organized into banks of 32 gpios,
   tnetv107x has a single space with arrays of registers for in, out,
   direction, etc.
 - davinci's controller has separate set/clear registers for output, tnetv107x
   has a single direct mapped register.

This patch does not yet add gpio irq support on this controller.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

TNETV107X is a Texas Instruments SOC that shares a number of common features
with the Davinci architecture.  Some of the key differences between
traditional Davincis and this new SOC are as follow:

1. The SOCs clock architecture includes a new spread-spectrum PLL.  Some
elements of the clock architecture are reused from Davinci (e.g. LPSC), but
the PLL related code is overridden using existing interfaces in "struct clk".

2. The MMR layout on this SOC is substantially different from Davinci.
Consequently, the fixed I/O map is a whole lot more convoluted (more so than
DA8xx).  The net impact here is that IO_ADDRESS() will not work on this SoC,
and therefore all mappings have to be through ioremap().
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Added definitions for tnetv107x uart base addresses, and modified base address
selection for kernel decompressor to check for tnetv107x machine type.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adopts a debug uart selection similar to the OMAP model.  During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart.  These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The touch screen controller in the TPS6507x chip needs values that are
dependent on the characteristics of the touch screen hardware being used
in the board design.  In addition, the board provides version information
that is exposed via the kernel input sub-system.
Signed-off-by: NTodd Fischer <todd.fischer@ridgerun.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

Add mfd structure which refrences sub-driver initialization data. For example,
for a giving hardware implementation, the voltage regulator sub-driver
initialization data provides the mapping betten a voltage regulator and what
the output voltage is being used for.
Signed-off-by: NTodd Fischer <todd.fischer@ridgerun.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

On some platforms like DM355, the number of EDMA parameter slots available
for EDMA_SLOT_ANY usage are few.  In such cases, if MMC/SD uses 16 slots
for each instance of MMC controller, then the number of slots available
for other modules will be very few.

By passing the number of EDMA slots to be used in MMC driver from platform
data, EDMA slots available for other purposes can be controlled.

Most of the platforms will not use this platform data variable.  But on
DM355, as the number of EDMA resources available is limited, the number of
scatter- gather segments used inside the MMC driver can be 8 (passed as
platform data) instead of 16.  On DM355, when the number of scatter-gather
segments was reduced to 8, I saw a performance difference of about
0.25-0.4 Mbytes/sec during write.  Read performance variations were
negligible.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Acked-by: NKevin Hilman <khilman@deeprootsystems.com>
Cc: <linux-mmc@vger.kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

DA8xx OHCI driver fails to load due to failing clk_get() call for the USB 2.0
clock. Arrange matching USB 2.0 clock by the clock name instead of the device.
(Adding another CLK() entry for "ohci.0" device won't do -- in the future I'll
also have to enable USB 2.0 clock to configure CPPI 4.1 module, in which case
I won't have any device at all.)
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

More complete AEMIF support for boards.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Added PINMUX configurations for the CLKOUT0 .. CLKOUT2
functions, for boards that want to use these clocks.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Board code may want to use them.
Signed-off-by: NThomas Koeller <thomas.koeller@baslerweb.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows for a more flexible ioremap() interception based on iotable
contents.

With this patch, the ioremap() interception code can properly translate
addresses only after davinci_soc_info has been initialized.  Consequently,
in soc-specific init functions, davinci_common_init() has to happen before any
ioremap() attempts. The da8xx init sequence has been suitably modified to meet
this restriction.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the pinmux implementation so as to ioremap() the pinmux
register area on first use.
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>