Add clock data for RNG module on AM33xx SoC.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

clkout2 comes out on the pad and is being used by various
external on-board peripherals like, Audio codecs and stuff.
So enable the clkout2 by default during init sequence itself.

Also, add the missing entry of "clkout2_ck" to the clock table.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Represent debugSS clock interface as provided in
CM_WKUP_DEBUGSS_CLKCTRL register, includes
	- Clock gate for optional DEBUG_CLKA and DBGSYSCLK
	- Clock Mux for TRC_PMD and STM_PMD
	- Clock divider for STM and TPIU
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

EHRPWM module requires explicit clock gating of TBCLK from control
module. Hence add TBCLK clock node in clock tree for EHRPWM modules.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
[bigeasy: remove CK_AM33XX]
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

It is required to enable respective clock-domain before
enabling any clock/module inside that clock-domain.

During common-clock migration, .clkdm_name field got missed
for "clkdiv32k_ick" clock, which leaves "clk_24mhz_clkdm"
unused; so it will be disabled even if childs of this clock-domain
is enabled, which keeps child modules in idle mode.

This fixes the kernel crash observed on AM335xEVM-SK platform,
where clkdiv32_ick clock is being used as a gpio debounce clock
and since clkdiv32k_ick is in idle mode it leads to below crash -

Crash Log:
==========
[    2.598347] Unhandled fault: external abort on non-linefetch (0x1028) at
0xfa1ac150
[    2.606434] Internal error: : 1028 [#1] SMP ARM
[    2.611207] Modules linked in:
[    2.614449] CPU: 0    Not tainted  (3.8.4-01382-g1f449cd-dirty #4)
[    2.620973] PC is at _set_gpio_debounce+0x60/0x104
[    2.626025] LR is at clk_enable+0x30/0x3c

Cc: stable@vger.kernel.org # v3.9
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

WDT1 module can take one of the below clocks as input functional
clock -
     - On-Chip 32K RC Osc [default/reset]
     - 32K from PRCM

The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec, so as a result, for example, timer which supposed
to get expired @60Sec, but will expire somewhere ~@40Sec, which is
not expected by any use-case.

The solution here is to switch the input clock-source to PRCM
generated 32K clock-source during boot-time itself.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Benoit Cousson <benoit.cousson@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>

Add clock data for for the SHA0 crypto module
on the am33xx SoC.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NMark A. Greer <mgreer@animalcreek.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add clock data for for the SHA0 crypto module
on the am33xx SoC.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NMark A. Greer <mgreer@animalcreek.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The patch removes all the CK_* which were used to identify the family of
processors for which the individual clocks belonged to. Instead now separate
lists are created based on the family of processors.

Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Tested-by: NVaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: NJon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register();
 updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

LCDC clock node is a one that does not have set rate capability. It
just passes on the rate that is sent downstream by it's parent. While
lcdc clock parent and it's grand parent - dpll_disp_m2_ck and
dpll_disp_ck has the capability to configure rate.

And the default rates provided by LCDC clock's ancestors are not
sufficient to obtain pixel clock for current LCDC use cases, hence
currently display would not work on AM335x SoC's (with driver
modifications in platfrom independent way).

Hence inform clock framework to propogate set rate for LCDC clock as
well as it's parent - dpll_disp_m2_ck. With this change, set rate on
LCDC clock would get propogated till dpll_disp_ck via dpll_disp_m2_ck,
hence allowing the driver (same driver is used in DaVinci too) to set
rates using LCDC clock without worrying about platform dependent clock
details.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

OMAP2/3/4 clock-tree data is migrated to common-clock framework,
so it is needed to do same for AM33XX device.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: replace omap2_init_clksel_parent() with
 omap2_clksel_find_parent_index(); modified to not use the AM33xx common
 clock data yet; updated patch description; reflowed the macros;
 updated DEFINE_STRUCT_CLK_HW_OMAP usage to include clkdm_name]
Signed-off-by: NMike Turquette <mturquette@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>