提交 78e52e02 编写于 作者: J J Keerthy 提交者: Paul Walmsley

ARM: OMAP2+: clock data: Remove CK_* flags

The patch removes all the CK_* which were used to identify the family of
processors for which the individual clocks belonged to. Instead now separate
lists are created based on the family of processors.

Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Tested-by: NVaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: NJon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register();
 updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
上级 a937536b
......@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
static struct omap_clk omap2420_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
CLK(NULL, "osc_ck", &osc_ck, CK_242X),
CLK(NULL, "sys_ck", &sys_ck, CK_242X),
CLK(NULL, "alt_ck", &alt_ck, CK_242X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
CLK(NULL, "dpll_ck", &dpll_ck),
CLK(NULL, "apll96_ck", &apll96_ck),
CLK(NULL, "apll54_ck", &apll54_ck),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
CLK(NULL, "core_ck", &core_ck, CK_242X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
CLK(NULL, "func_54m_ck", &func_54m_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "func_96m_ck", &func_96m_ck),
CLK(NULL, "func_48m_ck", &func_48m_ck),
CLK(NULL, "func_12m_ck", &func_12m_ck),
CLK(NULL, "sys_clkout_src", &sys_clkout_src),
CLK(NULL, "sys_clkout", &sys_clkout),
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
CLK(NULL, "sys_clkout2", &sys_clkout2),
CLK(NULL, "emul_ck", &emul_ck),
/* mpu domain clocks */
CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
CLK(NULL, "mpu_ck", &mpu_ck),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
CLK(NULL, "dsp_fck", &dsp_fck),
CLK(NULL, "dsp_ick", &dsp_ick),
CLK(NULL, "iva1_ifck", &iva1_ifck),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
CLK(NULL, "gfx_ick", &gfx_ick),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
CLK(NULL, "dss_ick", &dss_ick, CK_242X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
CLK("omapdss_dss", "ick", &dss_ick),
CLK(NULL, "dss_ick", &dss_ick),
CLK(NULL, "dss1_fck", &dss1_fck),
CLK(NULL, "dss2_fck", &dss2_fck),
CLK(NULL, "dss_54m_fck", &dss_54m_fck),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
CLK(NULL, "core_l3_ck", &core_l3_ck),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_242X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
CLK(NULL, "l4_ck", &l4_ck),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
CLK(NULL, "virt_prcm_set", &virt_prcm_set),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
CLK(NULL, "cam_fck", &cam_fck, CK_242X),
CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
CLK(NULL, "cam_ick", &cam_ick, CK_242X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
CLK(NULL, "fac_ick", &fac_ick, CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_242X),
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
CLK("omap-sham", "ick", &sha_ick, CK_242X),
CLK(NULL, "sha_ick", &sha_ick, CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_242X),
CLK(NULL, "rng_ick", &rng_ick, CK_242X),
CLK("omap-aes", "ick", &aes_ick, CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpios_ick", &gpios_ick),
CLK(NULL, "gpios_fck", &gpios_fck),
CLK("omap_wdt", "ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
CLK(NULL, "sync_32k_ick", &sync_32k_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK("omap24xxcam", "fck", &cam_fck),
CLK(NULL, "cam_fck", &cam_fck),
CLK("omap24xxcam", "ick", &cam_ick),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "wdt4_ick", &wdt4_ick),
CLK(NULL, "wdt4_fck", &wdt4_fck),
CLK(NULL, "wdt3_ick", &wdt3_ick),
CLK(NULL, "wdt3_fck", &wdt3_fck),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK("mmci-omap.0", "ick", &mmc_ick),
CLK(NULL, "mmc_ick", &mmc_ick),
CLK("mmci-omap.0", "fck", &mmc_fck),
CLK(NULL, "mmc_fck", &mmc_fck),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "fac_fck", &fac_fck),
CLK(NULL, "eac_ick", &eac_ick),
CLK(NULL, "eac_fck", &eac_fck),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap_hdq.0", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "i2c1_fck", &i2c1_fck),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2c2_fck", &i2c2_fck),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "sdma_fck", &sdma_fck),
CLK(NULL, "sdma_ick", &sdma_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "vlynq_ick", &vlynq_ick),
CLK(NULL, "vlynq_fck", &vlynq_fck),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
CLK(NULL, "sha_ick", &sha_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
CLK(NULL, "aes_ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "usb_fck", &usb_fck),
CLK("musb-hdrc", "fck", &osc_ck),
CLK(NULL, "timer_32k_ck", &func_32k_ck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "timer_ext_ck", &alt_ck),
CLK(NULL, "cpufreq_ck", &virt_prcm_set),
};
......@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
int __init omap2420_clk_init(void)
{
struct omap_clk *c;
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
rate_table = omap2420_rate_table;
......@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
omap2xxx_clkt_vps_check_bootloader_rates();
for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
omap2xxx_clkt_vps_late_init();
......
......@@ -1840,168 +1840,168 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
static struct omap_clk omap2430_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
CLK(NULL, "osc_ck", &osc_ck, CK_243X),
CLK("twl", "fck", &osc_ck, CK_243X),
CLK(NULL, "sys_ck", &sys_ck, CK_243X),
CLK(NULL, "alt_ck", &alt_ck, CK_243X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK("twl", "fck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
CLK(NULL, "dpll_ck", &dpll_ck),
CLK(NULL, "apll96_ck", &apll96_ck),
CLK(NULL, "apll54_ck", &apll54_ck),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
CLK(NULL, "core_ck", &core_ck, CK_243X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
CLK(NULL, "func_54m_ck", &func_54m_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "func_96m_ck", &func_96m_ck),
CLK(NULL, "func_48m_ck", &func_48m_ck),
CLK(NULL, "func_12m_ck", &func_12m_ck),
CLK(NULL, "sys_clkout_src", &sys_clkout_src),
CLK(NULL, "sys_clkout", &sys_clkout),
CLK(NULL, "emul_ck", &emul_ck),
/* mpu domain clocks */
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
CLK(NULL, "mpu_ck", &mpu_ck),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
CLK(NULL, "dsp_fck", &dsp_fck),
CLK(NULL, "iva2_1_ick", &iva2_1_ick),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
CLK(NULL, "gfx_ick", &gfx_ick),
/* Modem domain clocks */
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
CLK(NULL, "mdm_ick", &mdm_ick),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
CLK(NULL, "dss_ick", &dss_ick, CK_243X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
CLK("omapdss_dss", "ick", &dss_ick),
CLK(NULL, "dss_ick", &dss_ick),
CLK(NULL, "dss1_fck", &dss1_fck),
CLK(NULL, "dss2_fck", &dss2_fck),
CLK(NULL, "dss_54m_fck", &dss_54m_fck),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
CLK(NULL, "core_l3_ck", &core_l3_ck),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
CLK(NULL, "l4_ck", &l4_ck),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
CLK(NULL, "virt_prcm_set", &virt_prcm_set),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
CLK(NULL, "cam_fck", &cam_fck, CK_243X),
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
CLK(NULL, "cam_ick", &cam_ick, CK_243X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
CLK(NULL, "des_ick", &des_ick, CK_243X),
CLK("omap-sham", "ick", &sha_ick, CK_243X),
CLK("omap_rng", "ick", &rng_ick, CK_243X),
CLK(NULL, "rng_ick", &rng_ick, CK_243X),
CLK("omap-aes", "ick", &aes_ick, CK_243X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
CLK(NULL, "mcspi3_ick", &mcspi3_ick),
CLK(NULL, "mcspi3_fck", &mcspi3_fck),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpios_ick", &gpios_ick),
CLK(NULL, "gpios_fck", &gpios_fck),
CLK("omap_wdt", "ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
CLK(NULL, "sync_32k_ick", &sync_32k_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK(NULL, "icr_ick", &icr_ick),
CLK("omap24xxcam", "fck", &cam_fck),
CLK(NULL, "cam_fck", &cam_fck),
CLK("omap24xxcam", "ick", &cam_ick),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "wdt4_ick", &wdt4_ick),
CLK(NULL, "wdt4_fck", &wdt4_fck),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "fac_fck", &fac_fck),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap_hdq.1", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "i2chs1_fck", &i2chs1_fck),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2chs2_fck", &i2chs2_fck),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "sdma_fck", &sdma_fck),
CLK(NULL, "sdma_ick", &sdma_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "usb_fck", &usb_fck),
CLK("musb-omap2430", "ick", &usbhs_ick),
CLK(NULL, "usbhs_ick", &usbhs_ick),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
CLK(NULL, "mmchs1_ick", &mmchs1_ick),
CLK(NULL, "mmchs1_fck", &mmchs1_fck),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
CLK(NULL, "mmchs2_ick", &mmchs2_ick),
CLK(NULL, "mmchs2_fck", &mmchs2_fck),
CLK(NULL, "gpio5_ick", &gpio5_ick),
CLK(NULL, "gpio5_fck", &gpio5_fck),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
CLK(NULL, "timer_32k_ck", &func_32k_ck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "timer_ext_ck", &alt_ck),
CLK(NULL, "cpufreq_ck", &virt_prcm_set),
};
static const char *enable_init_clks[] = {
......@@ -2019,8 +2019,6 @@ static const char *enable_init_clks[] = {
int __init omap2430_clk_init(void)
{
struct omap_clk *c;
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
rate_table = omap2430_rate_table;
......@@ -2029,12 +2027,7 @@ int __init omap2430_clk_init(void)
omap2xxx_clkt_vps_check_bootloader_rates();
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
omap2xxx_clkt_vps_late_init();
......
......@@ -838,80 +838,80 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
* clkdev
*/
static struct omap_clk am33xx_clks[] = {
CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
CLK(NULL, "clk_32768_ck", &clk_32768_ck),
CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
CLK(NULL, "tclkin_ck", &tclkin_ck),
CLK(NULL, "dpll_core_ck", &dpll_core_ck),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
CLK("cpu0", NULL, &dpll_mpu_ck),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
CLK(NULL, "dpll_per_ck", &dpll_per_ck),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
CLK(NULL, "cefuse_fck", &cefuse_fck),
CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
CLK(NULL, "dcan0_fck", &dcan0_fck),
CLK("481cc000.d_can", NULL, &dcan0_fck),
CLK(NULL, "dcan1_fck", &dcan1_fck),
CLK("481d0000.d_can", NULL, &dcan1_fck),
CLK(NULL, "debugss_ick", &debugss_ick),
CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
CLK(NULL, "mcasp0_fck", &mcasp0_fck),
CLK(NULL, "mcasp1_fck", &mcasp1_fck),
CLK(NULL, "mmu_fck", &mmu_fck),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
CLK(NULL, "timer1_fck", &timer1_fck),
CLK(NULL, "timer2_fck", &timer2_fck),
CLK(NULL, "timer3_fck", &timer3_fck),
CLK(NULL, "timer4_fck", &timer4_fck),
CLK(NULL, "timer5_fck", &timer5_fck),
CLK(NULL, "timer6_fck", &timer6_fck),
CLK(NULL, "timer7_fck", &timer7_fck),
CLK(NULL, "usbotg_fck", &usbotg_fck),
CLK(NULL, "ieee5000_fck", &ieee5000_fck),
CLK(NULL, "wdt1_fck", &wdt1_fck),
CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
CLK(NULL, "l3_gclk", &l3_gclk),
CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
CLK(NULL, "l4hs_gclk", &l4hs_gclk),
CLK(NULL, "l3s_gclk", &l3s_gclk),
CLK(NULL, "l4fw_gclk", &l4fw_gclk),
CLK(NULL, "l4ls_gclk", &l4ls_gclk),
CLK(NULL, "clk_24mhz", &clk_24mhz),
CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
CLK(NULL, "lcd_gclk", &lcd_gclk),
CLK(NULL, "mmc_clk", &mmc_clk),
CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
};
......@@ -926,21 +926,10 @@ static const char *enable_init_clks[] = {
int __init am33xx_clk_init(void)
{
struct omap_clk *c;
u32 cpu_clkflg;
if (soc_is_am33xx()) {
if (soc_is_am33xx())
cpu_mask = RATE_IN_AM33XX;
cpu_clkflg = CK_AM33XX;
}
for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
omap2_clk_disable_autoidle_all();
......
......@@ -23,7 +23,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clk-private.h>
#include <asm/cpu.h>
......@@ -568,6 +568,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap_clocks_register - register an array of omap_clk
* @ocs: pointer to an array of omap_clk to register
*/
void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
{
struct omap_clk *c;
for (c = oclks; c < oclks + cnt; c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
/**
* omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
* @mpurate_ck_name: clk name of the clock to change rate
......
......@@ -27,9 +27,8 @@ struct omap_clk {
struct clk_lookup lk;
};
#define CLK(dev, con, ck, cp) \
#define CLK(dev, con, ck) \
{ \
.cpu = cp, \
.lk = { \
.dev_id = dev, \
.con_id = con, \
......@@ -37,22 +36,6 @@ struct omap_clk {
}, \
}
/* Platform flags for the clkdev-OMAP integration code */
#define CK_242X (1 << 0)
#define CK_243X (1 << 1) /* 243x, 253x */
#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 6)
#define CK_TI816X (1 << 7)
#define CK_446X (1 << 8)
#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
struct clockdomain;
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
......@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
#endif
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