ADMA errors are potentially data corrupting events; although we print
the register state, we do not usefully print the ADMA descriptors.
Worse than that, we print them by referencing their virtual address
which is meaningless when the register state gives us the DMA address
of the failing descriptor.

Print the ADMA descriptors giving their DMA addresses rather than their
virtual addresses, and print them using SDHCI_DUMP() rather than DBG().

We also do not show the correct value of the interrupt status register;
the register dump shows the current value, after we have cleared the
pending interrupts we are going to service.  What is more useful is to
print the interrupts that _were_ pending at the time the ADMA error was
encountered.  Fix that too.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Commit feb4eb06 ("firmware: bcm47xx_nvram: Correct size_t printf
format") was wrong, and changed a printout of 'header.len' - which is an
u32 type - to use '%zu'.

It apparently did pattern matching on the other case, where it printed
out 'nvram_len', which is indeed of type 'size_t'.

Rather than undoing the change, this just makes it use the variable that
the change seemed to expect to be used.

Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Paul Burton <paul.burton@mips.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The only caller of hisi_zip_vf_q_assign() is hidden in an #ifdef,
so the function causes a warning when CONFIG_PCI_IOV is disabled:

drivers/crypto/hisilicon/zip/zip_main.c:740:12: error: unused function 'hisi_zip_vf_q_assign' [-Werror,-Wunused-function]

Replace the #ifdef with an IS_ENABLED() check that leads to the
function being dropped based on the configuration.

Fixes: 79e09f30 ("crypto: hisilicon - add SRIOV support for ZIP")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

add_early_randomness() is called by hwrng_register() when the
hardware is added. If this hardware and its module are present
at boot, and if there is no data available the boot hangs until
data are available and can't be interrupted.

For instance, in the case of virtio-rng, in some cases the host can be
not able to provide enough entropy for all the guests.

We can have two easy ways to reproduce the problem but they rely on
misconfiguration of the hypervisor or the egd daemon:

- if virtio-rng device is configured to connect to the egd daemon of the
host but when the virtio-rng driver asks for data the daemon is not
connected,

- if virtio-rng device is configured to connect to the egd daemon of the
host but the egd daemon doesn't provide data.

The guest kernel will hang at boot until the virtio-rng driver provides
enough data.

To avoid that, call rng_get_data() in non-blocking mode (wait=0)
from add_early_randomness().
Signed-off-by: NLaurent Vivier <lvivier@redhat.com>
Fixes: d9e79726 ("hwrng: add randomness to system from rng...")
Cc: <stable@vger.kernel.org>
Reviewed-by: NTheodore Ts'o <tytso@mit.edu>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The return valude of add_comp_head() is int, but @head_size is size_t,
which is a unsigned type.

	size_t head_size;
	...
	if (head_size < 0)  // it will never work
		return -ENOMEM

Modify the type of @head_size to int, then change the type to size_t
when invoke hisi_zip_create_req() as a parameter.

Fixes: 62c455ca ("crypto: hisilicon - add HiSilicon ZIP accelerator support")
Signed-off-by: NYunfeng Ye <yeyunfeng@huawei.com>
Acked-by: NZhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

When dma_pool_zalloc() fail in sec_alloc_and_fill_hw_sgl(),
dma_pool_free() is invoked, but the parameters that sgl_current and
sgl_current->next_sgl is not match.

Using sec_free_hw_sgl() instead of the original free routine.

Fixes: 915e4e84 ("crypto: hisilicon - SEC security accelerator driver")
Signed-off-by: NYunfeng Ye <yeyunfeng@huawei.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

There are two problems in sec_free_hw_sgl():

First, when sgl_current->next is valid, @hw_sgl will be freed in the
first loop, but it free again after the loop.

Second, sgl_current and sgl_current->next_sgl is not match when
dma_pool_free() is invoked, the third parameter should be the dma
address of sgl_current, but sgl_current->next_sgl is the dma address
of next chain, so use sgl_current->next_sgl is wrong.

Fix this by deleting the last dma_pool_free() in sec_free_hw_sgl(),
modifying the condition for while loop, and matching the address for
dma_pool_free().

Fixes: 915e4e84 ("crypto: hisilicon - SEC security accelerator driver")
Signed-off-by: NYunfeng Ye <yeyunfeng@huawei.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

This patch fixes an unused variable warning from the compiler when the
driver is being compiled without PCI support in the kernel.

Fixes: 625f269a ("crypto: inside-secure - add support for...")
Signed-off-by: NPascal van Leeuwen <pvanleeuwen@verimatrix.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Add missing break statement in order to prevent the code from falling
through to case CRYPTO_ALG_TYPE_AHASH.

Fixes: aeb4c132 ("crypto: talitos - Convert to new AEAD interface")
Cc: stable@vger.kernel.org
Reported-by: Nkbuild test robot <lkp@intel.com>
Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: NChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

These recursive functions have checks for !clk being passed in, but the
callers are always looping through lists and therefore the pointers
can't be NULL. Drop the checks to simplify the code.
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org

Before commit e42ee610 ("of: Let of_for_each_phandle fallback to
non-negative cell_count") the iterator functions calling
of_for_each_phandle assumed a cell count of 0 if cells_name was NULL.
This corner case was missed when implementing the fallback logic in
e42ee610 and resulted in an endless loop.

Restore the old behaviour of of_count_phandle_with_args() and
of_parse_phandle_with_args() and add a check to
of_phandle_iterator_init() to prevent a similar failure as a safety
precaution. of_parse_phandle_with_args_map() doesn't need a similar fix
as cells_name isn't NULL there.

Affected drivers are:
 - drivers/base/power/domain.c
 - drivers/base/power/domain.c
 - drivers/clk/ti/clk-dra7-atl.c
 - drivers/hwmon/ibmpowernv.c
 - drivers/i2c/muxes/i2c-demux-pinctrl.c
 - drivers/iommu/mtk_iommu.c
 - drivers/net/ethernet/freescale/fman/mac.c
 - drivers/opp/of.c
 - drivers/perf/arm_dsu_pmu.c
 - drivers/regulator/of_regulator.c
 - drivers/remoteproc/imx_rproc.c
 - drivers/soc/rockchip/pm_domains.c
 - sound/soc/fsl/imx-audmix.c
 - sound/soc/fsl/imx-audmix.c
 - sound/soc/meson/axg-card.c
 - sound/soc/samsung/tm2_wm5110.c
 - sound/soc/samsung/tm2_wm5110.c

Thanks to Geert Uytterhoeven for reporting the issue, Peter Rosin for
helping pinpoint the actual problem and the testers for confirming this
fix.

Fixes: e42ee610 ("of: Let of_for_each_phandle fallback to non-negative cell_count")
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NRob Herring <robh@kernel.org>

pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.
Suggested-by: NJacky Bai <ping.bai@nxp.com>
Reviewed-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.

Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm")
Suggested-by: NJacky Bai <ping.bai@nxp.com>
Reviewed-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.

To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.

Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."

So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.

When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;

Fixes: 8646d4dc ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Add driver support for AP807 clock.
Signed-off-by: NBen Peled <bpeled@marvell.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Factor out the code that is only useful to AP806 so it will be easier
to support AP807. No functional changes.
Signed-off-by: NBen Peled <bpeled@marvell.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.
Signed-off-by: NOmri Itach <omrii@marvell.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

"SaR" means Sample at Reset. DIP switches can be changed on the board,
their states at reset time is available through a register read.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU
clocks.
Signed-off-by: NBen Peled <bpeled@marvell.com>
[<miquel.raynal@bootlin.com>: use device data instead of conditions on
the compatible]
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-5-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

This patch allows same flow to be executed on chips with different
register mappings like AP806 and, in the future, AP807.

Note: this patch has no functional effect, and only prepares the
driver for additional chips to be supported by retrieving the right
device data depenging on the compatible property.
Signed-off-by: NChristine Gharzuzi <chrisg@marvell.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-4-miquel.raynal@bootlin.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b005 ("clk: sprd: add adjustable pll support")
Signed-off-by: NChunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: NChunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.comAcked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Naming the glink edge device on the parent of_node short name causes
collisions when multiple remoteproc instances with only different unit
address are described on the platform_bus in DeviceTree.

Base the edge's name on the parent remoteproc's name instead, to ensure
that it's unique.
Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>

The adreno driver expects the "id" field of the returned clk_bulk_data
to be filled in with strings from the clock-names property.

But due to the use of kmalloc_array() in of_clk_bulk_get_all() it
receives a list of bogus pointers instead.

Zero-initialize the "id" field and attempt to populate with strings from
the clock-names property to resolve both these issues.

Fixes: 616e45df ("clk: add new APIs to operate on all available clocks")
Fixes: 8e3e791d ("drm/msm: Use generic bulk clock function")
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190913024029.2640-1-bjorn.andersson@linaro.orgReviewed-by: NJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Since the helper "owl_factor_helper_round_rate" is shared between factor
and composite clocks, using the factor clk specific helper function
like "hw_to_owl_factor" to access its members will create issues when
called from composite clk specific code. Hence, pass the "factor_hw"
struct pointer directly instead of fetching it using factor clk specific
helpers.

This issue has been observed when a composite clock like "sd0_clk" tried
to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
error.

While we are at it, let's rename the "clk_val_best" function to
"owl_clk_val_best" since this is an owl SoCs specific helper.

Fixes: 4bb78fc9 ("clk: actions: Add factor clock support")
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190916154546.24982-2-manivannan.sadhasivam@linaro.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Sometimes an extraneous "---help---" follows "help". That is probably a
copy&paste error stemming from their inconsistent use. Remove those.
Signed-off-by: NLubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.skSigned-off-by: NStephen Boyd <sboyd@kernel.org>

We leave a dangling pointer in each clk_core::parents array that has an
unregistered clk as a potential parent when that clk_core pointer is
freed by clk{_hw}_unregister(). It is impossible for the true parent of
a clk to be set with clk_set_parent() once the dangling pointer is left
in the cache because we compare parent pointers in
clk_fetch_parent_index() instead of checking for a matching clk name or
clk_hw pointer.

Before commit ede77858 ("clk: Remove global clk traversal on fetch
parent index"), we would check clk_hw pointers, which has a higher
chance of being the same between registration and unregistration, but it
can still be allocated and freed by the clk provider. In fact, this has
been a long standing problem since commit da0f0b2c ("clk: Correct
lookup logic in clk_fetch_parent_index()") where we stopped trying to
compare clk names and skipped over entries in the cache that weren't
NULL.

There are good (performance) reasons to not do the global tree lookup in
cases where the cache holds dangling pointers to parents that have been
unregistered. Let's take the performance hit on the uncommon
registration path instead. Loop through all the clk_core::parents arrays
when a clk is unregistered and set the entry to NULL when the parent
cache entry and clk being unregistered are the same pointer. This will
fix this problem and avoid the overhead for the "normal" case.

Based on a patch by Bjorn Andersson.

Fixes: da0f0b2c ("clk: Correct lookup logic in clk_fetch_parent_index()")
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190828181959.204401-1-sboyd@kernel.org

Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.
Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.
Signed-off-by: NWeiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>

Add pericfg clocks for MT8183, it's used when support USB
remote wakeup

Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.comAcked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The VPU firmware assume that the PLLD_PER isn't modified by the ARM core.
Otherwise this could cause firmware lookups. So mark the clock as critical
to avoid this.
Signed-off-by: NStefan Wahren <wahrenst@gmx.net>
Reviewed-by: NEric Anholt <eric@anholt.net>

The new BCM2711 supports an additional clock for the emmc2 block.
So add a new compatible and register this clock only for BCM2711.
Signed-off-by: NStefan Wahren <wahrenst@gmx.net>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NEric Anholt <eric@anholt.net>

In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we
extend the description with a SoC support flag. This approach avoids long
and mostly redundant lists of clock IDs. Since PLLH is specific to
BCM2835, we register only rest of the clocks as common to all SoC.
Suggested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NStefan Wahren <wahrenst@gmx.net>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NEric Anholt <eric@anholt.net>

The mailbox length is 0x1000 hence the max_register value is 0xFFC.

Fixes: c6a8b171 ("mailbox: qcom: Convert APCS IPC driver to use
regmap")
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

Add support of IPQ8074 with IPC register offset as 8.
Signed-off-by: NGokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

Use the correct macro when registering the platform device.
Co-developed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>

There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.
Co-developed-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>