1. 03 10月, 2020 1 次提交
  2. 19 9月, 2020 3 次提交
    • Y
      dpaa2-eth: support PTP Sync packet one-step timestamping · c5521189
      Yangbo Lu 提交于
      This patch is to add PTP sync packet one-step timestamping support.
      Before egress, one-step timestamping enablement needs,
      
      - Enabling timestamp and FAS (Frame Annotation Status) in
        dpni buffer layout.
      
      - Write timestamp to frame annotation and set PTP bit in
        FAS to mark as one-step timestamping event.
      
      - Enabling one-step timestamping by dpni_set_single_step_cfg()
        API, with offset provided to insert correction time on frame.
        The offset must respect all MAC headers, VLAN tags and other
        protocol headers accordingly. The correction field update can
        consider delays up to one second. So PTP frame needs to be
        filtered and parsed, and written timestamp into Sync frame
        originTimestamp field.
      
      The operation of API dpni_set_single_step_cfg() has to be done
      when no one-step timestamping frames are in flight. So we have
      to make sure the last one-step timestamping frame has already
      been transmitted on hardware before starting to send the current
      one. The resolution is,
      
      - Utilize skb->cb[0] to mark timestamping request per packet.
        If it is one-step timestamping PTP sync packet, queue to skb queue.
        If not, transmit immediately.
      
      - Schedule a work to transmit skbs in skb queue.
      
      - mutex lock is used to ensure the last one-step timestamping packet
        has already been transmitted on hardware through TX confirmation queue
        before transmitting current packet.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c5521189
    • Y
      dpaa2-eth: utilize skb->cb[0] for hardware timestamping · 1cf773bd
      Yangbo Lu 提交于
      This patch is a preparation for next hardware one-step timestamping
      support. For DPAA2, the one step timestamping configuration on
      hardware registers has to be done when there is no one-step timestamping
      packet in flight. So we will have to use workqueue and skb queue
      for such packets transmitting, to make sure waiting the last packet has
      already been sent on hardware, and starting to transmit the current one.
      
      So the tx timestamping flag in private data may not reflect the actual
      request for the one-step timestamping packets of skb queue. This also
      affects skb headroom allocation. Let's use skb->cb[0] to mark the
      timestamping request for each skb.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1cf773bd
    • Y
      dpaa2-eth: define a global ptp_qoriq structure pointer · d21c784c
      Yangbo Lu 提交于
      Define a global ptp_qoriq structure pointer, and export to use.
      The ptp clock operations will be used in dpaa2-eth driver.
      For example, supporting one step timestamping needs to write
      current time to hardware frame annotation before sending and
      then hardware inserts the delay time on frame during sending.
      So in driver, at least clock gettime operation will be needed
      to make sure right time is written to hardware frame annotation
      for one step timestamping.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d21c784c
  3. 22 7月, 2020 1 次提交
  4. 30 6月, 2020 2 次提交
  5. 02 6月, 2020 7 次提交
  6. 17 5月, 2020 1 次提交
  7. 16 5月, 2020 1 次提交
  8. 08 5月, 2020 1 次提交
  9. 26 4月, 2020 1 次提交
  10. 23 4月, 2020 3 次提交
  11. 01 11月, 2019 1 次提交
    • I
      dpaa2-eth: add MAC/PHY support through phylink · 71947923
      Ioana Ciornei 提交于
      The dpaa2-eth driver now has support for connecting to its associated
      PHY device found through standard OF bindings.
      
      This happens when the DPNI object (that the driver probes on) gets
      connected to a DPMAC. When that happens, the device tree is looked up by
      the DPMAC ID, and the associated PHY bindings are found.
      
      The old logic of handling the net device's link state by hand still
      needs to be kept, as the DPNI can be connected to other devices on the
      bus than a DPMAC: other DPNI, DPSW ports, etc. This logic is only
      engaged when there is no DPMAC (and therefore no phylink instance)
      attached.
      
      The MC firmware support multiple type of DPMAC links: TYPE_FIXED,
      TYPE_PHY. The TYPE_FIXED mode does not require any DPMAC management from
      Linux side, and as such, the driver will not handle such a DPMAC.
      
      Although PHYLINK typically handles SFP cages and in-band AN modes, for
      the moment the driver only supports the RGMII interfaces found on the
      LX2160A. Support for other modes will come later.
      Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      71947923
  12. 07 10月, 2019 1 次提交
  13. 30 8月, 2019 1 次提交
    • I
      dpaa2-eth: Add pause frame support · 8eb3cef8
      Ioana Radulescu 提交于
      Starting with firmware version MC10.18.0, we have support for
      L2 flow control. Asymmetrical configuration (Rx or Tx only) is
      supported, but not pause frame autonegotioation.
      
      Pause frame configuration is done via ethtool. By default, we start
      with flow control enabled on both Rx and Tx. Changes are propagated
      to hardware through firmware commands, using two flags (PAUSE,
      ASYM_PAUSE) to specify Rx and Tx pause configuration, as follows:
      
      PAUSE | ASYM_PAUSE | Rx pause | Tx pause
      ----------------------------------------
        0   |     0      | disabled | disabled
        0   |     1      | disabled | enabled
        1   |     0      | enabled  | enabled
        1   |     1      | enabled  | disabled
      
      The hardware can automatically send pause frames when the number
      of buffers in the pool goes below a predefined threshold. Due to
      this, flow control is incompatible with Rx frame queue taildrop
      (both mechanisms target the case when processing of ingress
      frames can't keep up with the Rx rate; for large frames, the number
      of buffers in the pool may never get low enough to trigger pause
      frames as long as taildrop is enabled). So we set pause frame
      generation and Rx FQ taildrop as mutually exclusive.
      Signed-off-by: NIoana Radulescu <ruxandra.radulescu@nxp.com>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8eb3cef8
  14. 13 6月, 2019 2 次提交
  15. 27 5月, 2019 1 次提交
  16. 17 4月, 2019 3 次提交
  17. 27 3月, 2019 1 次提交
  18. 04 3月, 2019 2 次提交
  19. 07 2月, 2019 3 次提交
  20. 20 1月, 2019 2 次提交
  21. 29 11月, 2018 2 次提交