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  1. 21 5月, 2007 4 次提交
  3. 14 5月, 2007 2 次提交
    • P
      sh: Kill off pmb slab cache destructor. · 38c425f6
      由 Paul Mundt 提交于 
      This is the last remaining slab destructor in the kernel, which
we kill off and move the resultant list tracking logic up to
the pmb_alloc()/pmb_free() paths.

As Christoph Lameter pointed out, it's potentially unsafe to be
taking the list lock in the destructor anyways, so this is also
more fundamentally correct.

With this in place, we're all set for killing off slab destructors
from the kernel entirely.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      38c425f6
    • P
      sh: Shut up compiler warnings in __do_page_fault(). · b8947444
      由 Paul Mundt 提交于 
      GCC doesn't seem to be able to figure this one out for
itself, so just shut it up..

  CC      arch/sh/mm/fault.o
arch/sh/mm/fault.c: In function '__do_page_fault':
arch/sh/mm/fault.c:288: warning: 'ptl' may be used uninitialized in this function
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      b8947444
  5. 09 5月, 2007 5 次提交
  7. 07 5月, 2007 4 次提交
  9. 05 3月, 2007 1 次提交
  11. 14 2月, 2007 1 次提交
  13. 13 2月, 2007 10 次提交
  15. 12 2月, 2007 1 次提交
  17. 12 12月, 2006 3 次提交
  19. 09 12月, 2006 1 次提交
  21. 08 12月, 2006 2 次提交
    • C
      [PATCH] slab: remove kmem_cache_t · e18b890b
      由 Christoph Lameter 提交于 
      Replace all uses of kmem_cache_t with struct kmem_cache.

The patch was generated using the following script:

	#!/bin/sh
	#
	# Replace one string by another in all the kernel sources.
	#

	set -e

	for file in `find * -name "*.c" -o -name "*.h"|xargs grep -l $1`; do
		quilt add $file
		sed -e "1,\$s/$1/$2/g" $file >/tmp/$$
		mv /tmp/$$ $file
		quilt refresh
	done

The script was run like this

	sh replace kmem_cache_t "struct kmem_cache"
Signed-off-by: NChristoph Lameter <clameter@sgi.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e18b890b
    • C
      [PATCH] shared page table for hugetlb page · 39dde65c
      由 Chen, Kenneth W 提交于 
      Following up with the work on shared page table done by Dave McCracken.  This
set of patch target shared page table for hugetlb memory only.

The shared page table is particular useful in the situation of large number of
independent processes sharing large shared memory segments.  In the normal
page case, the amount of memory saved from process' page table is quite
significant.  For hugetlb, the saving on page table memory is not the primary
objective (as hugetlb itself already cuts down page table overhead
significantly), instead, the purpose of using shared page table on hugetlb is
to allow faster TLB refill and smaller cache pollution upon TLB miss.

With PT sharing, pte entries are shared among hundreds of processes, the cache
consumption used by all the page table is smaller and in return, application
gets much higher cache hit ratio.  One other effect is that cache hit ratio
with hardware page walker hitting on pte in cache will be higher and this
helps to reduce tlb miss latency.  These two effects contribute to higher
application performance.
Signed-off-by: NKen Chen <kenneth.w.chen@intel.com>
Acked-by: NHugh Dickins <hugh@veritas.com>
Cc: Dave McCracken <dmccr@us.ibm.com>
Cc: William Lee Irwin III <wli@holomorphy.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Adam Litke <agl@us.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      39dde65c
  23. 06 12月, 2006 6 次提交
    • J
      sh: sh775x/titan fixes for irq header changes. · ea0f8fea
      由 Jamie Lenehan 提交于 
      The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.

 - adds an ipr_idx to the ipr_data and uses a function in the subtype
   code to calculate the address of the IPR registers

 - adds a function to enable individual interrupt mode for externals
   in the subtype code and calls that from the titan board code
   instead of doing it directly.

 - I changed the shift in the ipr_data to be the actual # of bits to
   shift, instead of the numnber / 4 - made it easier to match with
   the manual.
Signed-off-by: NJamie Lenehan <lenehan@twibble.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ea0f8fea
    • P
      sh: stacktrace/lockdep/irqflags tracing support. · afbfb52e
      由 Paul Mundt 提交于 
      Wire up all of the essentials for lockdep..
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      afbfb52e
    • P
      sh: Get the PGD right in oops case with 64-bit PTEs. · bca7c207
      由 Paul Mundt 提交于 
      Previously this was using a static pgd shift in the reporting
code, simply flip this to PGDIR_SHIFT which does the right
thing depending on varying PTE magnitudes on the SH-X2 MMU.

While we're at it, and since it's been recently added, use
get_TTB() for fetching the TTB, rather than the open coded
instructions.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      bca7c207
    • P
      sh: Fixup various PAGE_SIZE == 4096 assumptions. · 510c72ad
      由 Paul Mundt 提交于 
      There were a number of places that made evil PAGE_SIZE == 4k
assumptions that ended up breaking when trying to play with
8k and 64k page sizes, this fixes those up.

The most significant change is the way we load THREAD_SIZE,
previously this was done via:

	mov	#(THREAD_SIZE >> 8), reg
	shll8	reg

to avoid a memory access and allow the immediate load. With
a 64k PAGE_SIZE, we're out of range for the immediate load
size without resorting to special instructions available in
later ISAs (movi20s and so on). The "workaround" for this is
to bump up the shift to 10 and insert a shll2, which gives a
bit more flexibility while still being much cheaper than a
memory access.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      510c72ad
    • S
      sh: TLB miss fast-path optimizations. · 9b3a53ab
      由 Stuart Menefy 提交于 
      Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      9b3a53ab
    • S
      sh: pmd rework. · 99a596f9
      由 Stuart Menefy 提交于 
      Remove extra bits from the pmd structure and store a kernel logical
address rather than a physical address. This allows it to be directly
dereferenced. Another piece of wierdness inherited from x86.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      99a596f9