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  1. 01 10月, 2009 1 次提交
  3. 24 9月, 2009 4 次提交
  5. 22 9月, 2009 2 次提交
  7. 18 9月, 2009 2 次提交
  9. 17 9月, 2009 5 次提交
  11. 15 9月, 2009 1 次提交
  13. 14 9月, 2009 1 次提交
  15. 12 9月, 2009 1 次提交
    • J
      ASoC: Clean up error handling in MPC5200 DMA setup · 33d7f778
      由 Julia Lawall 提交于 
      Error handling code following a kzalloc should free the allocated data.
Error handling code following an ioremap should iounmap the allocated data.

The semantic match that finds the first problem is as follows:
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@r exists@
local idexpression x;
statement S;
expression E;
identifier f,f1,l;
position p1,p2;
expression *ptr != NULL;
@@

x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
...
if (x == NULL) S
<... when != x
     when != if (...) { <+...x...+> }
(
x->f1 = E
|
 (x->f1 == NULL || ...)
|
 f(...,x->f1,...)
)
...>
(
 return \(0\|<+...x...+>\|ptr\);
|
 return@p2 ...;
)

@script:python@
p1 << r.p1;
p2 << r.p2;
@@

print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
// </smpl>
Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      33d7f778
  17. 09 9月, 2009 1 次提交
    • M
      ASoC: au1x: PSC-AC97 bugfixes · cdc65fbe
      由 Manuel Lauss 提交于 
      This patch fixes the following bugs:

- only reprogram bitdepth if it has changed since last call to hw_params.
- add locking inside ac97_read/write functions:
  When reprogramming sample depth, the ac97 unit has to be disabled,
  which should not be done in the middle of codec register accesses.

- retry timed-out codec register accesses.

- wait for status bits to set/clear when starting/stopping various
  functional blocks; very important after reenabling AC97 unit else
  sound may be distorted (e.g. high-pitch noise in 1kHz sine wave).

- clear fifos before/after starting/stopping RX/TX.

- longer timeouts waiting for PSC/AC97 ready after cold reset
  with certain codecs this can take ridiculous amounts of time.

Run-tested on various Au1200 platforms with various codecs.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      cdc65fbe
  19. 08 9月, 2009 1 次提交
  21. 07 9月, 2009 1 次提交
  23. 05 9月, 2009 1 次提交
  25. 03 9月, 2009 1 次提交
  27. 01 9月, 2009 2 次提交
  29. 29 8月, 2009 1 次提交
    • J
      ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI · d2c0bdaa
      由 Jarkko Nikula 提交于 
      The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.

Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.

Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.
Signed-off-by: NJarkko Nikula <jhnikula@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      d2c0bdaa
  31. 28 8月, 2009 1 次提交
  33. 26 8月, 2009 5 次提交
  35. 25 8月, 2009 7 次提交
  37. 24 8月, 2009 2 次提交