1. 12 2月, 2017 1 次提交
  2. 03 2月, 2017 2 次提交
    • A
      i40e: add interrupt rate limit verbosity · 33084060
      Alan Brady 提交于
      Due to the resolution of the register controlling interrupt rate
      limiting, setting certain values for the interrupt rate limit make it
      appear as though the limiting is not completely accurate.  The problem
      is that the interrupt rate limit is getting rounded down to the nearest
      multiple of 4.  This patch fixes the problem by adding some feedback to
      the user as to the actual interrupt rate limit being used when it
      differs from the requested limit.  Without this patch setting interrupt
      rate limits may appear to behave inaccurately.
      
      Change-ID: I3093cf3f2d437d35a4c4f4bb5af5ce1b85ab21b7
      Signed-off-by: NAlan Brady <alan.brady@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      33084060
    • A
      i40e: refactor macro INTRL_USEC_TO_REG · 1c0e6a36
      Alan Brady 提交于
      This patch refactors the macro INTRL_USEC_TO_REG into a static inline
      function and fixes a couple subtle bugs caused by the macro.
      
      This patch fixes a bug which was caused by passing a bad register value
      to the firmware.  If enabling interrupt rate limiting, a non-zero value
      for the rate limit must be used.  Otherwise the firmware sets the
      interrupt rate limit to the maximum value.  Due to the limited
      resolution of the register, attempting to set a value of 1, 2, or 3
      would be rounded down to 0 and limiting was left enabled, causing
      unexpected behavior.
      
      This patch also fixes a possible bug in which using the macro itself can
      introduce unintended side-affects because the macro argument is used
      more than once in the macro definition (e.g. a variable post-increment
      argument would perform a double increment on the variable).
      
      Without this patch, attempting to set interrupt rate limits of 1, 2, or
      3 results in unexpected behavior and future use of this macro could
      cause subtle bugs.
      
      Change-Id: I83ac842de0ca9c86761923d6e3a4d7b1b95f2b3f
      Signed-off-by: NAlan Brady <alan.brady@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      1c0e6a36
  3. 07 12月, 2016 3 次提交
  4. 03 12月, 2016 4 次提交
    • J
      i40e/i40evf: replace for memcpy with single memcpy call in ethtool · e5d32205
      Jacob Keller 提交于
      memcpy replaced with single memcpy call in ethtool.
      
      Change-ID: I3f5bef6bcc593412c56592c6459784db41575a0a
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      e5d32205
    • H
      i40e: Fix for ethtool Supported link modes · 4ad9f4f9
      Harshitha Ramamurthy 提交于
      This patch fixes the problem where the ethtool Supported link
      modes list backplane interfaces on X722 devices for 10GbE with
      SFP+ and Cortina retimer. This patch fixes the problem by setting
      and using a flag for this particular device since the backplane
      interface is only between the internal PHY and the retimer and it
      should not be seen by the user as they cannot use it.
      Without this patch, the user wrongly thinks that backplane interfaces
      are supported on their device when they actually are not.
      
      Change-ID: I3882bc2928431d48a2db03a51a713a1f681a79e9
      Signed-off-by: NHarshitha Ramamurthy <harshitha.ramamurthy@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      4ad9f4f9
    • T
      i40e: fix panic on SPARC while changing num of desc · 2f7679ee
      Tushar Dave 提交于
      On SPARC, writel() should not be used to write directly to memory
      address but only to memory mapped I/O address otherwise it causes
      data access exception.
      
      Commit 147e81ec ("i40e: Test memory before ethtool alloc
      succeeds") introduced a code that uses memory address to fake the HW
      tail address and attempt to write to that address using writel()
      causes kernel panic on SPARC. The issue is reproduced while changing
      number of descriptors using ethtool.
      
      This change resolves the panic by using HW read-only memory mapped
      I/O register to fake HW tail address instead memory address.
      
      e.g.
      > ethtool -G eth2 tx 2048 rx 2048
      i40e 0000:03:00.2 eth2: Changing Tx descriptor count from 512 to 2048.
      i40e 0000:03:00.2 eth2: Changing Rx descriptor count from 512 to 2048
      sun4v_data_access_exception: ADDR[fff8001f9734a000] CTX[0000]
      TYPE[0004], going.
                    \|/ ____ \|/
                    "@'/ .. \`@"
                    /_| \__/ |_\
                       \__U_/
      ethtool(3273): Dax [#1]
      CPU: 9 PID: 3273 Comm: ethtool Tainted: G            E
      4.8.0-linux-net_temp+ #7
      task: fff8001f96d7a660 task.stack: fff8001f97348000
      TSTATE: 0000009911001601 TPC: 00000000103189e4 TNPC: 00000000103189e8 Y:
      00000000    Tainted: G            E
      TPC: <i40e_alloc_rx_buffers+0x124/0x260 [i40e]>
      g0: fff8001f4eb64000 g1: 00000000000007ff g2: fff8001f9734b92c g3:
      00203e0000000000
      g4: fff8001f96d7a660 g5: fff8001fa6704000 g6: fff8001f97348000 g7:
      0000000000000001
      o0: 0006000046706928 o1: 00000000db3e2000 o2: fff8001f00000000 o3:
      0000000000002000
      o4: 0000000000002000 o5: 0000000000000001 sp: fff8001f9734afc1 ret_pc:
      0000000010318a64
      RPC: <i40e_alloc_rx_buffers+0x1a4/0x260 [i40e]>
      l0: fff8001f4e8bffe0 l1: fff8001f4e8cffe0 l2: 00000000000007ff l3:
      00000000ff000000
      l4: 0000000000ff0000 l5: 000000000000ff00 l6: 0000000000cda6a8 l7:
      0000000000e822f0
      i0: fff8001f96380000 i1: 0000000000000000 i2: 00203edb00000000 i3:
      0006000046706928
      i4: 0000000002086320 i5: 0000000000e82370 i6: fff8001f9734b071 i7:
      00000000103062d4
      I7: <i40e_set_ringparam+0x3b4/0x540 [i40e]>
      Call Trace:
       [00000000103062d4] i40e_set_ringparam+0x3b4/0x540 [i40e]
       [000000000094e2f8] dev_ethtool+0x898/0xbe0
       [0000000000965570] dev_ioctl+0x250/0x300
       [0000000000923800] sock_do_ioctl+0x40/0x60
       [000000000092427c] sock_ioctl+0x7c/0x280
       [00000000005ef040] vfs_ioctl+0x20/0x60
       [00000000005ef5d4] do_vfs_ioctl+0x194/0x4c0
       [00000000005ef974] SyS_ioctl+0x74/0xa0
       [0000000000406214] linux_sparc_syscall+0x34/0x44
      Disabling lock debugging due to kernel taint
      Caller[00000000103062d4]: i40e_set_ringparam+0x3b4/0x540 [i40e]
      Caller[000000000094e2f8]: dev_ethtool+0x898/0xbe0
      Caller[0000000000965570]: dev_ioctl+0x250/0x300
      Caller[0000000000923800]: sock_do_ioctl+0x40/0x60
      Caller[000000000092427c]: sock_ioctl+0x7c/0x280
      Caller[00000000005ef040]: vfs_ioctl+0x20/0x60
      Caller[00000000005ef5d4]: do_vfs_ioctl+0x194/0x4c0
      Caller[00000000005ef974]: SyS_ioctl+0x74/0xa0
      Caller[0000000000406214]: linux_sparc_syscall+0x34/0x44
      Caller[0000000000107154]: 0x107154
      Instruction DUMP: e43620c8
       e436204a  c45e2038
      <c2a083a0> 82102000
       81cfe008  90086001
       82102000  81cfe008
      
      Kernel panic - not syncing: Fatal exception
      Signed-off-by: NTushar Dave <tushar.n.dave@oracle.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      2f7679ee
    • J
      i40e: avoid duplicate private flags definitions · d182a5ca
      Jacob Keller 提交于
      Separate the global private flags and the regular private flags per
      interface into two arrays. Future additions of private flags will not
      need to be duplicated which may lead to buggy code. Also rename
      "i40e_priv_flags_strings_gl" to "i40e_gl_priv_flags_strings" for
      clarity, as it reads more naturally.
      
      Change-ID: I68caef3c9954eb7da342d7f9d20f2873186f2758
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      d182a5ca
  5. 01 11月, 2016 2 次提交
  6. 29 10月, 2016 2 次提交
    • A
      i40e: Clean up handling of msglevel flags and debug parameter · 5d4ca23e
      Alexander Duyck 提交于
      So the i40e driver had a really convoluted configuration for how to handle
      the debug flags contained in msg_level.  Part of the issue is that the
      driver has its own 32 bit mask that it was using to track a separate set of
      debug features.  From what I can tell it was trying to use the upper 4 bits
      to determine if the value was meant to represent a bit-mask or the numeric
      value provided by debug level.
      
      What this patch does is clean this up by compressing those 4 bits into bit
      31, as a result we just have to perform a check against the value being
      negative to determine if we are looking at a debug level (positive), or a
      debug mask (negative).  The debug level will populate the msg_level, and
      the debug mask will populate the debug_mask in the hardware struct.
      
      I added similar logic for ethtool.  If the value being provided has bit 31
      set we assume the value being provided is a debug mask, otherwise we assume
      it is a msg_enable mask.  For displaying we only provide the msg_enable,
      and if debug_mask is in use we will print it to the dmesg log.
      
      Lastly I removed the debugfs interface.  It is redundant with what we
      already have in ethtool and really doesn't belong anyway.
      Signed-off-by: NAlexander Duyck <alexander.h.duyck@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      5d4ca23e
    • J
      i40e: Make struct i40e_stats const · fe180a5e
      Joe Perches 提交于
      Move some data to text
      
      $ size drivers/net/ethernet/intel/i40e/i40e_ethtool.o*
         text	   data	    bss	    dec	    hex	filename
        25012	      0	     32	  25044	   61d4	drivers/net/ethernet/intel/i40e/i40e_ethtool.o.new
        22868	   2120	     32	  25020	   61bc	drivers/net/ethernet/intel/i40e/i40e_ethtool.o.old
      Signed-off-by: NJoe Perches <joe@perches.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      fe180a5e
  7. 25 9月, 2016 2 次提交
    • J
      i40evf: support queue-specific settings for interrupt moderation · 65e87c03
      Jacob Keller 提交于
      In commit a75e8005 ("i40e: queue-specific settings for interrupt
      moderation") the i40e driver gained support for setting interrupt
      moderation values per queue. This patch adds support for this feature
      to the i40evf driver as well. In addition, a few changes are made to
      the i40e implementation to add function header documentation comments,
      as well.
      
      This behaves in a similar fashion to the implementation in i40e. Thus,
      requesting the moderation value when no queue is provided will report
      queue 0 value, while setting the value without a queue will set all
      queues at once.
      
      Change-ID: I1f310a57c8e6c84a8524c178d44d1b7a6d3a848e
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      65e87c03
    • J
      i40e: cleanup ATR auto_disable_flags use · 234dc4e6
      Jacob Keller 提交于
      Some locations that disable ATR accidentally used the "full" disable by
      disabling the flag in the standard flags field. This incorrectly forces
      ATR off permanently instead of temporarily disabling it. In addition,
      some code locations accidentally set the ATR flag enabled when they only
      meant to clear the auto_disable_flags. This results in ignoring the
      user's ethtool private flag settings.
      
      Additionally, when disabling ATR via ethtool, we did not perform a flush
      of the FD table. This results in the previously assigned ATR rules still
      functioning which was not expected.
      
      Cleanup all these areas so that automatic disable uses only the
      auto_disable_flag. Fix the flush code so that we can trigger a flush
      even when we've disabled ATR and SB support, as otherwise the flush
      doesn't work. Fix ethtool setting to actually request a flush. Fix
      NETIF_F_NTUPLE flag to only clear the auto_disable setting and not
      enable the full feature.
      
      Change-ID: Ib2486111f8031bd16943e9308757b276305c03b5
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      234dc4e6
  8. 23 9月, 2016 1 次提交
    • A
      i40e: fix setting user defined RSS hash key · f1582351
      Alan Brady 提交于
      Previously, when using ethtool to change the RSS hash key, ethtool would
      report back saying the old key was still being used and no error was
      reported.  It was unclear whether it was being reported incorrectly or
      being set incorrectly.  Debugging revealed 'i40e_set_rxfh()' returned
      zero immediately instead of setting the key because a user defined
      indirection table is not supplied when changing the hash key.
      
      This fix instead changes it such that if an indirection table is not
      supplied, then a default one is created and the hash key is now
      correctly set.
      
      Change-ID: Iddb621897ecf208650272b7ee46702cad7b69a71
      Signed-off-by: NAlan Brady <alan.brady@intel.com>
      Tested-by: NAndrew Bowers <andrewx.bowers@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      f1582351
  9. 20 8月, 2016 1 次提交
  10. 19 8月, 2016 2 次提交
  11. 22 7月, 2016 2 次提交
  12. 28 6月, 2016 2 次提交
  13. 14 5月, 2016 3 次提交
  14. 06 5月, 2016 3 次提交
  15. 26 4月, 2016 1 次提交
  16. 06 4月, 2016 1 次提交
  17. 05 4月, 2016 1 次提交
  18. 20 2月, 2016 3 次提交
  19. 19 2月, 2016 2 次提交
  20. 18 2月, 2016 2 次提交