The pin controllers also use the two oscillators for debouncing. Add them
to the DTs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NChen-Yu Tsai <wens@csie.org>

Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
and newer.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add the new DAI blocks to the device tree.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This commit adds all the mod1 clocks available on A20 to its device
tree. This list was created by looking at the A20 user manual.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add NAND Flash controller node definition to the A20 SoC.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NAleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

No functional change. Re-order sun7i pinctrl nodes alphabetically.
Signed-off-by: NAleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Update the simplefb nodes for hdmi / tv-encoder out to point to
tcon0_ch1 instead of tcon0_ch0 as tcon clock.

While at it fix the clocks lines being longer than 80 chars.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Enable the display and TCON clocks that are needed to drive the display
engine, tcon and TV encoders.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Fix pll3x2 and pll7x2 not having a parent clock, specifically this
fixes the kernel turning of pll3 while simplefb is using it when
uboot has configured things to use pll3x2 as lcd ch clk parent.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we've a clock node describing pll3 we must add it to the
simplefb nodes clocks lists to avoid it getting turned off when
simplefb is used.

This fixes the screen going black when using simplefb.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Enable pll3 and pll7 clocks that are needed by display clocks.
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Seems like dram_gate 5 was forgotten when DRAM gating driver was added.

Add it.

Cc: stable@vger.kernel.org
Fixes: 0b4bf5a5 (ARM: dts: sun7i: Add DRAM gates)
Signed-off-by: NPriit Laes <plaes@plaes.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the SPDIF transceiver controller block to the A20 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the SPDIF clock to the A20 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the SPDIF TX pin to the A20 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The video engine has its own module clock, which also includes a
reset control for it.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The DRAM gates controls direct memory access for some peripherals.
These peripherals include the display pipeline, so add the required
gates to the simplefb nodes as well.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 SoC includes the Allwinner audio codec, capable of both 24-bit
playback and capture. This commit adds a device node for it.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

The audio codec functional clock is a child of PLL2 and is used to control
the audio rate, enable it in the DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

The A20 uses the PLL2 as the audio PLL, which is the parent of all the
other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

This patch add support to the keypad clock on sun7i
Signed-off-by: NYassin Jaffer <yassinjaffer@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum
CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise
the voltage for the lowest operating point to 1.0 volts in order to stay
within the SoC specifications. It is an undervolted setting that isn't
stable across all SoCs and boards out there.

Cc: <stable@vger.kernel.org> # v4.0+
Fixes: d96b7161 ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi")
Signed-off-by: NTimo Sigurdsson <public_timo.s@silentcreek.de>
Acked-by: NIain Paton <ipaton0@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The current DTs were setting the cell size to 2, but used the default xlate
function that was assuming an interrupt cell size of 1, leading to the
second part of the cell (the flags) being ignored, while we were having an
inconsistent binding between the interrupts and gpio (that could also be
used as interrupts).

That "binding" doesn't work either with newer SoCs that have multiple irq
banks.

Now that we fixed the pinctrl driver to handle this like it should always
have been handled, convert the DT users, and while we're at it, remove the
size-cells property of PIO that is completely useless.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.

This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Add a node for the otg/drc usb controller to sun7i-a20.dtsi
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Tested-by: NHans de Goede <hdegoede@redhat.com>

This patch reverts commit ccb4ada2 ("ARM: dts: sun7i: Add A20 SRAM and
SRAM controller"), commit e6f51e4b ("ARM: dts: sun5i: Add A13 and A10s
SRAM and SRAM controller") and commit 6d92b80f ("ARM: dts: sun4i: Add
A10 SRAM and SRAM controller").

The bindings have been changed in the SRAM driver, and we need to
change the DT accordingly.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux
entry for these.
Signed-off-by: NMichael Ring <mail@michael-ring.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The pinctrl groups for SPI until now were also adding the chip selects in
the SPI pinctrl group.

This was causing a few issues, since a board was forced to use a random
number of chipselects, even though it might use one of these chip selects
for another pin.

The number of chipselects defined was also not the same from one group to
another because of different needs at the time these groups have been
introduced, resulting in no clear view from the board DTS on what exactly
is being muxed, which even might change in the future.

Solve this by creating different pinctrl groups for the chipselects and the
standard SPI pins (CLK, MOSI and MISO) so that we fix both issues.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

A few lines (probably copy pasted) have an indentation mixing tabs and
spaces that triggers a checkpatch warning.

Fix those, and while we're at it, fix the space-indented sections.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

A few lines in our DTSIs are over the 80 characters limit, making
checkpatch complain about that.

If possible (and relevant), wrap these lines to 80 characters.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The FSF address triggers a warning on checkpatch, saying that the FSF
license is already present in the Linux source code, and that it has
already changed in the past.

Remove it from our DT, as suggested.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Currently none of the target boards nor the driver supports
IR TX. However this pin is used in a few instances as a GPIO.
Split the pin ctrl descriptions so that only the IR RX is
configured to be used.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The clock driver now supports a muxable ahb clock. Update the dtsi
with the proper compatible and add the new parent clocks.

This also adds the new pll6/4 output for pll6 on sun7i-a20. The
output is not used on sun4/5i.

Also use assigned-clocks to reparent ahb to pll6. We want ahb to
have a stable, non-changing clock rate. cpu/axi clock rate changes
as a result of newly added cpufreq support.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
[hdegoede@redhat.com: Do not change soc node name, change compatible to
 sun4i-a10-sram-controller to match the driver change]
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Sometimes we need to specify non-probably information for sdio devices in the
devicetree, this is done through child nodes addressed by the reg property,
whereby the reg property refers to the sdio function number, see;
Documentation/devicetree/bindings/mmc/mmc.txt

This commit adds the necessary address- and size-cells properties to the mmc
controller nodes in the dtsi files, so that dts files needing such a child
node do not need to specify these themselves.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The touchscreen controller in the A13 and later has a different temperature
curve than the one in the original A10, change the compatible for the A13 and
later so that the kernel will use the correct curve.
Reported-by: NTong Zhang <lovewilliam@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Without proper regulator support for individual boards, it is dangerous
to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase
the frequency without the accompanying voltage increase, resulting in
an unstable system.

Remove them for now. We can revisit them with the new version of OPP
bindings, which support boost settings and frequency ranges, among
other things.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Commit f77d55a3 ("serial: 8250_dw: get index of serial line from DT
aliases") made the serial driver now use the serial aliases to get the tty
number, pointing out that our aliases have been wrong all along.

Remove them from the DTSI and add custom ones in the relevant boards.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>