1. 29 10月, 2019 5 次提交
    • J
      RDMA/mlx5: Do not race with mlx5_ib_invalidate_range during create and destroy · 09689703
      Jason Gunthorpe 提交于
      For creation, as soon as the umem_odp is created the notifier can be
      called, however the underlying MR may not have been setup yet. This would
      cause problems if mlx5_ib_invalidate_range() runs. There is some
      confusing/ulocked/racy code that might by trying to solve this, but
      without locks it isn't going to work right.
      
      Instead trivially solve the problem by short-circuiting the invalidation
      if there are not yet any DMA mapped pages. By definition there is nothing
      to invalidate in this case.
      
      The create code will have the umem fully setup before anything is DMA
      mapped, and npages is fully locked by the umem_mutex.
      
      For destroy, invalidate the entire MR at the HW to stop DMA then DMA unmap
      the pages before destroying the MR. This drives npages to zero and
      prevents similar racing with invalidate while the MR is undergoing
      destruction.
      
      Arguably it would be better if the umem was created after the MR and
      destroyed before, but that would require a big rework of the MR code.
      
      Fixes: 6aec21f6 ("IB/mlx5: Page faults handling infrastructure")
      Link: https://lore.kernel.org/r/20191009160934.3143-15-jgg@ziepe.caReviewed-by: NArtemy Kovalyov <artemyko@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      09689703
    • J
      RDMA/mlx5: Rework implicit ODP destroy · 5256edcb
      Jason Gunthorpe 提交于
      Use SRCU in a sensible way by removing all MRs in the implicit tree from
      the two xarrays (the update operation), then a synchronize, followed by a
      normal single threaded teardown.
      
      This is only a little unusual from the normal pattern as there can still
      be some work pending in the unbound wq that may also require a workqueue
      flush. This is tracked with a single atomic, consolidating the redundant
      existing atomics and wait queue.
      
      For understand-ability the entire ODP implicit create/destroy flow now
      largely exists in a single pair of functions within odp.c, with a few
      support functions for tearing down an unused child.
      
      Link: https://lore.kernel.org/r/20191009160934.3143-13-jgg@ziepe.caReviewed-by: NArtemy Kovalyov <artemyko@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      5256edcb
    • J
      RDMA/mlx5: Use an xarray for the children of an implicit ODP · 423f52d6
      Jason Gunthorpe 提交于
      Currently the child leaves are stored in the shared interval tree and
      every lookup for a child must be done under the interval tree rwsem.
      
      This is further complicated by dropping the rwsem during iteration (ie the
      odp_lookup(), odp_next() pattern), which requires a very tricky an
      difficult to understand locking scheme with SRCU.
      
      Instead reserve the interval tree for the exclusive use of the mmu
      notifier related code in umem_odp.c and give each implicit MR a xarray
      containing all the child MRs.
      
      Since the size of each child is 1GB of VA, a 1 level xarray will index 64G
      of VA, and a 2 level will index 2TB, making xarray a much better
      data structure choice than an interval tree.
      
      The locking properties of xarray will be used in the next patches to
      rework the implicit ODP locking scheme into something simpler.
      
      At this point, the xarray is locked by the implicit MR's umem_mutex, and
      read can also be locked by the odp_srcu.
      
      Link: https://lore.kernel.org/r/20191009160934.3143-10-jgg@ziepe.caReviewed-by: NArtemy Kovalyov <artemyko@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      423f52d6
    • J
      RDMA/mlx5: Use a dedicated mkey xarray for ODP · 806b101b
      Jason Gunthorpe 提交于
      There is a per device xarray storing mkeys that is used to store every
      mkey in the system. However, this xarray is now only read by ODP for
      certain ODP designated MRs (ODP, implicit ODP, MW, DEVX_INDIRECT).
      
      Create an xarray only for use by ODP, that only contains ODP related
      MKeys. This xarray is protected by SRCU and all erases are protected by a
      synchronize.
      
      This improves performance:
      
       - All MRs in the odp_mkeys xarray are ODP MRs, so some tests for is_odp()
         can be deleted. The xarray will also consume fewer nodes.
      
       - normal MR's are never mixed with ODP MRs in a SRCU data structure so
         performance sucking synchronize_srcu() on every MR destruction is not
         needed.
      
       - No smp_load_acquire(live) and xa_load() double barrier on read
      
      Due to the SRCU locking scheme care must be taken with the placement of
      the xa_store(). Once it completes the MR is immediately visible to other
      threads and only through a xa_erase() & synchronize_srcu() cycle could it
      be destroyed.
      
      Link: https://lore.kernel.org/r/20191009160934.3143-4-jgg@ziepe.caReviewed-by: NArtemy Kovalyov <artemyko@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      806b101b
    • J
      RDMA/mlx5: Split sig_err MR data into its own xarray · 50211ec9
      Jason Gunthorpe 提交于
      The locking model for signature is completely different than ODP, do not
      share the same xarray that relies on SRCU locking to support ODP.
      
      Simply store the active mlx5_core_sig_ctx's in an xarray when signature
      MRs are created and rely on trivial xarray locking to serialize
      everything.
      
      The overhead of storing only a handful of SIG related MRs is going to be
      much less than an xarray full of every mkey.
      
      Link: https://lore.kernel.org/r/20191009160934.3143-3-jgg@ziepe.caReviewed-by: NArtemy Kovalyov <artemyko@mellanox.com>
      Reviewed-by: NMax Gurtovoy <maxg@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      50211ec9
  2. 23 10月, 2019 5 次提交
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  21. 09 4月, 2019 1 次提交