1. 29 10月, 2016 1 次提交
    • H
      regulator: core: silence warning: "VDD1: ramp_delay not set" · ba14fa1a
      H. Nikolaus Schaller 提交于
      commit 73e705bf ("regulator: core: Add set_voltage_time op")
      
      introduced a new rdev_warn() if the ramp_delay is 0.
      
      Apparently, on omap3/twl4030 platforms with dynamic voltage
      management this results in non-ending spurious messages like
      
      [  511.143066] VDD1: ramp_delay not set
      [  511.662322] VDD1: ramp_delay not set
      [  513.903625] VDD1: ramp_delay not set
      [  514.222198] VDD1: ramp_delay not set
      [  517.062835] VDD1: ramp_delay not set
      [  517.382568] VDD1: ramp_delay not set
      [  520.142791] VDD1: ramp_delay not set
      [  520.502593] VDD1: ramp_delay not set
      [  523.062896] VDD1: ramp_delay not set
      [  523.362701] VDD1: ramp_delay not set
      [  526.143035] VDD1: ramp_delay not set
      
      I have observed this on GTA04 while it is reported to occur on
      N900 as well: https://bugzilla.kernel.org/show_bug.cgi?id=178371
      
      This patch makes the warning appear only in debugging mode.
      Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      ba14fa1a
  2. 27 9月, 2016 2 次提交
  3. 26 9月, 2016 1 次提交
  4. 25 9月, 2016 2 次提交
    • J
      regulator: core: don't return error with inadequate reason · 57776617
      Joonwoo Park 提交于
      drms_uA_update() always returns failure when it cannot find regulator's
      input voltage.  But if hardware supports load configuration with
      ops->set_load() and the input regulator isn't specified with valid reason
      such as the input regulator is battery, not finding input voltage is
      normal so such case should not return with an error.
      
      Avoid such inadequate error return by checking input/output voltages
      only when drms_uA_update() is about to configure load with enum based
      ops->set_mode().
      
      Cc: Liam Girdwood <lgirdwood@gmail.com>
      Cc: Mark Brown <broonie@kernel.org>
      Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: NJoonwoo Park <joonwoop@codeaurora.org>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      57776617
    • J
      regulator: tps65910: Work around silicon erratum SWCZ010 · 8f9165c9
      Jan Remmet 提交于
      http://www.ti.com/lit/pdf/SWCZ010:
        DCDC o/p voltage can go higher than programmed value
      
      Impact:
      VDDI, VDD2, and VIO output programmed voltage level can go higher than
      expected or crash, when coming out of PFM to PWM mode or using DVFS.
      
      Description:
      When DCDC CLK SYNC bits are 11/01:
      * VIO 3-MHz oscillator is the source clock of the digital core and input
        clock of VDD1 and VDD2
      * Turn-on of VDD1 and VDD2 HSD PFETis synchronized or at a constant
        phase shift
      * Current pulled though VCC1+VCC2 is Iload(VDD1) + Iload(VDD2)
      * The 3 HSD PFET will be turned-on at the same time, causing the highest
        possible switching noise on the application. This noise level depends
        on the layout, the VBAT level, and the load current. The noise level
        increases with improper layout.
      
      When DCDC CLK SYNC bits are 00:
      * VIO 3-MHz oscillator is the source clock of digital core
      * VDD1 and VDD2 are running on their own 3-MHz oscillator
      * Current pulled though VCC1+VCC2 average of Iload(VDD1) + Iload(VDD2)
      * The switching noise of the 3 SMPS will be randomly spread over time,
        causing lower overall switching noise.
      
      Workaround:
      Set DCDCCTRL_REG[1:0]= 00.
      Signed-off-by: NJan Remmet <j.remmet@phytec.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      8f9165c9
  5. 17 9月, 2016 3 次提交
  6. 15 9月, 2016 1 次提交
  7. 13 9月, 2016 1 次提交
  8. 02 9月, 2016 1 次提交
  9. 31 8月, 2016 3 次提交
  10. 23 8月, 2016 1 次提交
  11. 17 8月, 2016 2 次提交
  12. 16 8月, 2016 1 次提交
  13. 15 8月, 2016 1 次提交
  14. 11 8月, 2016 1 次提交
  15. 05 8月, 2016 2 次提交
  16. 25 7月, 2016 1 次提交
  17. 21 7月, 2016 1 次提交
    • S
      regulator: da9053/52: Fix incorrectly stated minimum and maximum voltage limits · 707319b6
      Steve Twiss 提交于
      This fix alters the minimum and maximum BUCK voltage limits for DA9052 and
      DA9053. It does so for the following cases:
      
      DA9052
      - BUCK3 (MEM)
         min: 0.925V -> 0.950V
         max: 2.500V -> 2.525V
      
      DA9053
      - BUCK3 (MEM)
         min: 0.925V -> 0.950V
         max: 2.500V -> 2.525V
      - BUCK4 (PERI)
         min: 0.925V -> 0.950V
         max: 2.500V -> 2.525V
      
      The voltage range remains the same, but the limits are shifted by +0.025V.
      
      This change is provided on DA9052:MEM, DA9053:MEM and DA9053:PERI
      and is a voltage difference of 0.025V, compared to those measured before
      this fix is applied. The patch has the effect of decreasing *all* measured
      voltages on those BUCKs when compared against the previously measured
      values for the same software voltage request.
      
      For example, with this fix applied for DA9052:MEM, DA9053:MEM and
      DA9053:PERI, the following is true.
      
      Because the previous software defined slot 0 as being 0.925V, if a request
      for 0.950V was previously sent, the slot 1 voltage would have been used.
      This would have corresponded to an actual measured voltage of 0.975V. But,
      with this patch fix, and with slot 0 properly aligned to 0.950V, if a
      voltage of 0.950V is requested by software, a measured value of 0.950V will
      be provided.
      Tested-by: NSteve Twiss <stwiss.opensource@diasemi.com>
      Signed-off-by: NSteve Twiss <stwiss.opensource@diasemi.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      707319b6
  18. 20 7月, 2016 2 次提交
  19. 18 7月, 2016 1 次提交
  20. 15 7月, 2016 2 次提交
  21. 12 7月, 2016 3 次提交
  22. 11 7月, 2016 4 次提交
  23. 07 7月, 2016 1 次提交
    • D
      regulator: pwm: Fix regulator ramp delay for continuous mode · c2588393
      Douglas Anderson 提交于
      The original commit adding support for continuous voltage mode didn't
      handle the regulator ramp delay properly.  It treated the delay as a
      fixed delay in uS despite the property being defined as uV / uS.  Let's
      adjust it.  Luckily there appear to be no users of this ramp delay for
      PWM regulators (as per grepping through device trees in linuxnext).
      
      Note also that the upper bound of usleep_range probably shouldn't be a
      full 1 ms longer than the lower bound since I've seen plenty of hardware
      with a ramp rate of ~5000 uS / uV and for small jumps the total delays
      are in the tens of uS.  1000 is way too much.  We'll try to be dynamic
      and use 10%.
      
      NOTE: This commit doesn't add support for regulator-enable-ramp-delay.
      That could be done in a future patch when someone has a user of that
      featre.
      
      Though this patch is shows as "fixing" a bug, there are no actual known
      users of continuous mode PWM regulator w/ ramp delay in mainline and so
      this likely won't have any effect on anyone unless they are working
      out-of-tree with private patches.  For anyone in this state, it is
      highly encouraged to also pick Boris Brezillon's WIP patches to get
      yourself a reliable and glitch-free regulator.
      
      Fixes: 4773be18 ("regulator: pwm-regulator: Add support for continuous-voltage")
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      c2588393
  24. 30 6月, 2016 2 次提交