1. 30 3月, 2015 1 次提交
  2. 22 11月, 2014 2 次提交
  3. 18 7月, 2014 1 次提交
  4. 05 3月, 2014 2 次提交
    • A
      ARM: imx: add suspend in ocram support for i.mx6q · df595746
      Anson Huang 提交于
      When system enter suspend, we can set the DDR IO to
      high-Z state to save DDR IOs' power consumption, this
      operation can save many power(from ~26mA@1.5V to ~15mA@1.5V,
      measured on i.MX6Q SabreSD board, R25) of DDR IOs. To
      achieve that, we need to copy the suspend code to ocram
      and run the low level hardware related code(set DDR IOs
      to high-Z state) in ocram.
      
      If there is no ocram space available, then system will
      still do suspend in external DDR, hence no DDR IOs will
      be set to high-Z.
      
      The OCRAM usage layout is as below,
      
      ocram suspend region(4K currently):
      ======================== high address ======================
                                    .
                                    .
                                    .
                                    ^
                                    ^
                                    ^
                            imx6_suspend code
                   PM_INFO structure(imx6_cpu_pm_info)
      ======================== low address =======================
      Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      df595746
    • A
      ARM: imx: add cpuidle support for i.mx6sl · 751f7e99
      Anson Huang 提交于
      Add cpuidle support for i.MX6SL, currently only support
      two cpuidle levels(ARM wfi and WAIT mode), and add software
      workaround for WAIT mode errata as below:
      
      ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
                during WAIT mode entry process could cause cache memory
                corruption.
      
      Software workaround:
          To prevent this issue from occurring, software should ensure that
      the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
      entering WAIT mode.
      Signed-off-by: NAnson Huang <b20788@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      751f7e99
  5. 31 12月, 2013 2 次提交
  6. 21 10月, 2013 4 次提交
  7. 30 9月, 2013 1 次提交
  8. 16 8月, 2013 1 次提交
  9. 17 6月, 2013 2 次提交