- 03 4月, 2019 1 次提交
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由 Angus Ainslie (Purism) 提交于
Fix a typo in the compatible string Signed-off-by: NAngus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: NDaniel Baluta <daniel.baluta@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 29 3月, 2019 1 次提交
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由 Fabio Estevam 提交于
thermal-zones node does not have any register properties and thus shouldn't be placed inside the bus. Move thermal-zones node from soc node to root node in order to fix the following build warning with W=1: arch/arm64/boot/dts/freescale/imx8mq.dtsi:305.18-364.6: Warning (simple_bus_reg): /soc@0/bus@30000000/thermal-zones: missing or empty reg/ranges property Signed-off-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 22 3月, 2019 2 次提交
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由 Fabio Estevam 提交于
Move opp-table node from soc node to root node. opp-table node does not have any register properties and thus shouldn't be placed inside the bus. This fixes the following build warnings with W=1: arch/arm64/boot/dts/freescale/imx8mq.dtsi:687.28-703.5: Warning (simple_bus_reg): /soc@0/opp-table: missing or empty reg/ranges property Fixes: 64d26f8c ("arm64: dts: imx8mq: Add the opp table and cores opp properties") Signed-off-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Angus Ainslie (Purism) 提交于
Add the imx8mq TMU (Thermal management unit) nodes for CPU, GPU, and VPU. Signed-off-by: NAngus Ainslie (Purism) <angus@akkea.ca> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 20 3月, 2019 2 次提交
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由 Daniel Baluta 提交于
SAI2 is part of AIPS-3 memory region. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Daniel Baluta 提交于
SDMA1 is part of AIPS-3 region and SDMA2 is part of AIPS-1 region. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 19 3月, 2019 4 次提交
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由 Anson Huang 提交于
i.MX8MQ has clock gate for each GPIO bank, add clock info to GPIO node for clock management. Signed-off-by: NAnson Huang <Anson.Huang@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
Add the 0.8GHz and 1GHz opps. According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Carlo Caione 提交于
Add the node for the OTP controller. Signed-off-by: NCarlo Caione <ccaione@baylibre.com> Reviewed-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 11 2月, 2019 5 次提交
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由 Lucas Stach 提交于
The peripheral bus on the i.MX8MQ is still limited to 32bits, so we need to declare the usable range for device DMA operations, as the DRAM will extend across the 32bit boundary if more than 3GB are installed. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Carlo Caione 提交于
Add the node for the ARM Performance Monitor Units. Signed-off-by: NCarlo Caione <ccaione@baylibre.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Abel Vesa 提交于
Add RTC support for i.MX8MQ. Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Tested-by: NChris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Carlo Caione 提交于
Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3 memory range to accommodate the QuadSPI-memory region. Signed-off-by: NCarlo Caione <ccaione@baylibre.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Fabio Estevam 提交于
Add support for the three ECSPI ports present on i.MX8MQ. Signed-off-by: NFabio Estevam <festevam@gmail.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 01 2月, 2019 3 次提交
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由 Lucas Stach 提交于
It adds USB device and phy nodes for imx8mq SoC. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Lucas Stach 提交于
The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Carlo Caione 提交于
The boot from eMMC is currently broken on the NXP i.MX8MQ EVK board. When trying to boot from eMMC it fails with: ... [ 1.271938] mmc1: Tuning failed, falling back to fixed sampling clock [ 1.287429] print_req_error: I/O error, dev mmcblk1, sector 1 flags 0 [ 1.306833] mmc1: Tuning failed, falling back to fixed sampling clock [ 1.322325] print_req_error: I/O error, dev mmcblk1, sector 2 flags 0 [ 1.329559] Buffer I/O error on dev mmcblk1, logical block 0, async page read [ 1.336714] mmcblk1: unable to read partition table ... The problem is the result of a partial misconfiguration of the pins and the missing assigned clock rate. Fixes: 9079aca4 ("arm64: add support for i.MX8M EVK board") Signed-off-by: NCarlo Caione <ccaione@baylibre.com> Tested-by: NChris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: NFabio Estevam <festevam@gmail.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 16 1月, 2019 2 次提交
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由 Lucas Stach 提交于
This adds support for the power domain controller found on the i.MX8MQ SoC. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Guido Günther 提交于
We can reuse the pwm from fsl,imx27-pwm as with other imx SOCs. Signed-off-by: NGuido Günther <agx@sigxcpu.org> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 11 1月, 2019 1 次提交
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由 Lucas Stach 提交于
The were added at the end of the AIPS1 address space, while they are in fact in the middle. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 16 12月, 2018 2 次提交
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Lucas Stach 提交于
This adds the basic DTS for the i.MX8MQ. For now only the following peripherals are supported: - IOMUXC (pin controller) - CCM (clock controller) - GPIO - UART - uSDHC (SD/eMMC controller) - FEC (ethernet controller) - i2c This is enough to get a very basic board support up and running. One known limitation is that the driver for the GPC interrupt controller is still missing, rendering the CPU sleep states unusable as there is nothing waking them up anymore. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Reviewed-by: NDong Aisheng <Aisheng.dong@nxp.com> Signed-off-by: NAbel Vesa <abel.vesa@nxp.com> Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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