1. 23 7月, 2016 1 次提交
  2. 04 7月, 2016 6 次提交
  3. 28 6月, 2016 1 次提交
  4. 23 6月, 2016 4 次提交
  5. 22 6月, 2016 3 次提交
  6. 10 6月, 2016 12 次提交
  7. 03 6月, 2016 3 次提交
  8. 13 5月, 2016 1 次提交
    • N
      ARM: OMAP5 / DRA7: Introduce workaround for 801819 · c0053bd5
      Nishanth Menon 提交于
      Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
      that "A livelock can occur in the L2 cache arbitration that might
      prevent a snoop from completing. Under certain conditions this can
      cause the system to deadlock. "
      
      Recommended workaround is as follows:
      Do both of the following:
      
      1) Do not use the write-back no-allocate memory type.
      2) Do not issue write-back cacheable stores at any time when the cache
      is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
      is implementation defined whether cacheable stores update the cache when
      the cache is disabled it is not expected that any portable code will
      execute cacheable stores when the cache is disabled.
      
      For implementations of Cortex-A15 configured without the “L2 arbitration
      register slice” option (typically one or two core systems), you must
      also do the following:
      
      3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
      
      So, we provide an option to disable write streaming on OMAP5 and DRA7.
      It is a rare condition to occur and may be enabled selectively based
      on platform acceptance of risk.
      
      Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
      is set to 0.
      
      Based on ARM errata Document revision 18.0 (22 Nov 2013)
      
      Note: the configuration for the workaround needs to be done with
      each CPU bringup, since CPU0 bringup is done by bootloader, it is
      recommended to have the workaround in the bootloader, kernel also does
      ensure that CPU0 has the workaround and makes the workaround active
      when CPU1 gets active.
      
      With CONFIG_SMP disabled, it is expected to be done by the bootloader.
      
      This does show significant degradation in synthetic tests such as
      mbw (https://packages.qa.debian.org/m/mbw.html)
      mbw -n 100 100|grep AVG (on a test platform)
      Without enabling the erratum:
      AVG Method: MEMCPY  Elapsed: 0.13406  MiB: 100.00000  Copy: 745.913 MiB/s
      AVG Method: DUMB    Elapsed: 0.06746  MiB: 100.00000  Copy: 1482.357 MiB/s
      AVG Method: MCBLOCK Elapsed: 0.03058  MiB: 100.00000  Copy: 3270.569 MiB/s
      After enabling the erratum:
      AVG Method: MEMCPY  Elapsed: 0.13757  MiB: 100.00000  Copy: 726.913 MiB/s
      AVG Method: DUMB    Elapsed: 0.12024  MiB: 100.00000  Copy: 831.668 MiB/s
      AVG Method: MCBLOCK Elapsed: 0.09243  MiB: 100.00000  Copy: 1081.942 MiB/s
      
      Most benchmarks are designed for specific performance analysis, so
      overall usecase must be considered before making a decision to
      enable/disable the erratum workaround.
      
      Pending internal investigation, the erratum is kept disabled by default.
      
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Suggested-by: NRichard Woodruff <r-woodruff2@ti.com>
      Suggested-by: NBrad Griffis <bgriffis@ti.com>
      Signed-off-by: NNishanth Menon <nm@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      c0053bd5
  9. 29 4月, 2016 2 次提交
  10. 25 4月, 2016 1 次提交
  11. 19 4月, 2016 1 次提交
  12. 15 4月, 2016 3 次提交
  13. 14 4月, 2016 2 次提交
    • D
      ARM: OMAP3: Fix external abort on 36xx waking from off mode idle · 1560d158
      Dave Gerlach 提交于
      Depending on timing during the resume path from off mode on 36xx, we may
      see external aborts. These seem to be caused by the following:
      
      - OMAP3 Advisory 1.62 "MPU Cannot Exit from Standby" says we need to
        disable intc autoidle before WFI
      
      - DM3730 Advisory 1.106 "MPU Leaves MSTANDBY State Before IDLEREQ of
        Interrupt Controller is Released" says we need to wait before
        accessing intc
      
      omap3_intc_resume_idle restores the intc autoidle for all resume paths,
      however in the resume path from off mode only it is also being restored
      by omap_intc_restore_context before this call to omap3_intc_resume_idle
      happens. The second restore of the intc autoidle in this path is what
      appears to be causing the external abort so for the off mode resume path
      let's rely on omap_intc_restore_context to restore intc autoidle, and
      for all other paths let omap3_intc_resume_idle handle it as it is now.
      Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      1560d158
    • A
      ARM: OMAP2+: wakeupgen: Add comment for unhandled FROZEN transitions · 814a9586
      Anna-Maria Gleixner 提交于
      FROZEN hotplug notifiers are not handled and do not have to be. Insert
      a comment to remember that the lack of the FROZEN transitions is no
      accident.
      
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Santosh Shilimkar <ssantosh@kernel.org>
      Cc: linux-omap@vger.kernel.org
      Signed-off-by: NAnna-Maria Gleixner <anna-maria@linutronix.de>
      Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      814a9586