- 23 7月, 2016 1 次提交
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由 Sebastian Reichel 提交于
Add missing sysconfig/sysstatus information to OMAP3 hwmod. The information has been checked against OMAP34xx and OMAP36xx TRM. Without this change DSI block is not reset during boot, which is required for working Nokia N950 display. Signed-off-by: NSebastian Reichel <sre@kernel.org> Cc: stable@vger.kernel.org Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 04 7月, 2016 6 次提交
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由 Tero Kristo 提交于
If the module has no clkctrl register defined, module_wait_ready should not try to access this. This can potentially cause an illegal register access, and result in bad idle reporting also. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
The previous implementation was racy in many locations, where the current status of the clockdomain was read out, some operations were executed, and the previous status info was used afterwards to decide next state for the clockdomain. Instead, fix the implementation of the allow_idle / deny_idle APIs to properly have usecounting support. This allows clean handling internally within the clockdomain core, and simplifies the usage also within hwmod. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
With the introduction of hwmod module clocks, the name of the hwmod main clk may not be available before hwmod setup, as hwmod setup may lookup the main clock dynamically based on the hwmod name. Thus, change the order of hwmod setup and main clock handling for the timer code, to make sure the main clock is going to be available. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
With the transition to hwmod module clocks, all hwmods will have their main clocks named <hwmod_name>_mod_ck. Use this info to fetch main_clk, and use it if found. Also, if a main_clk is found based on the hwmod name, disable the direct PRCM modulemode access from hwmod. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
This avoids the need to add most of the clock aliases under drivers/clk/ti/clk-xyz.c files. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
I found one more make randconfig build error with the recent SMP kexec changes. We need the mpuss now always available early. Fixes: 0573b957 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec") Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 28 6月, 2016 1 次提交
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由 Tony Lindgren 提交于
Looks like I only partially fixed up things if CONFIG_SMP is not set for the recent kexec changes. We don't have boot_secondary available without SMP as reported by Arnd. Fixes: 0573b957 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec") Reported-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 6月, 2016 4 次提交
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由 Tony Lindgren 提交于
Kexec needs omap4_cpu_kill, otherwise kexec will produce on SMP: kexec_load failed: Invalid argument Acked-by: NSantosh Shilimkar <ssantosh@kernel.org> Tested-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
We need to reset CPU1 properly for kexec when booting different kernel versions. Otherwise CPU1 will attempt to boot the the previous kernel's start_secondary(). Note that the restctrl register is different from the low-power mode wakeup register CPU1_WAKEUP_NS_PA_ADDR. We need to configure both. Let's fix the issue by defining SoC specific data to initialize things in a more generic way. And let's also standardize omap-smp.c to use soc_is instead of cpu_is while at it. Acked-by: NSantosh Shilimkar <ssantosh@kernel.org> Tested-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Kexec booted kernels on omap4 will hang early during the boot if the booted kernel is different version from the previous kernel. This is because the previous kernel may have configured low-power mode using CPU1_WAKEUP_NS_PA_ADDR. In that case it points to the previous kernel's omap4_secondary_startup(), and CPU1 can be in low power mode from the previous kernel. When the new kernel configures the CPU1 clockdomain, CPU1 can wake from low power state prematurely during omap44xx_clockdomains_init() running random code. Let's fix the issue by configuring CPU1_WAKEUP_NS_PA_ADDR before we call omap44xx_clockdomains_init(). Note that this is very early during the init, and we will do proper CPU1 reset during SMP init a bit later on in omap4_smp_prepare_cpus(). And we need to do this when SMP is not enabled as the previous kernel may have had it enabled. Acked-by: NSantosh Shilimkar <ssantosh@kernel.org> Tested-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Prepare things for making kexec work on SMP omap variants by initializing SARM RAM base early. This allows us to configure CPU1 for kexec in case the previous kernel has put CPU1 in low power mode. Note that this should not prevent moving other SAR RAM code to live under drivers. However for kexec, we will need this very early. Acked-by: NSantosh Shilimkar <ssantosh@kernel.org> Tested-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 22 6月, 2016 3 次提交
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由 Keerthy 提交于
As per the TRM: http://www.ti.com/lit/ug/spruh73m/spruh73m.pdf offset 0x4 is reserved for PRM_PER. Hence removing the wrongly defined address offset. Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Ben Dooks 提交于
The ti81xx_rtc_hwmod is not exported, or declared outside the file arch/arm/mach-omap2/omap_hwmod_81xx_data.c so make it static to avoid the following warning: arch/arm/mach-omap2/omap_hwmod_81xx_data.c:246:19: warning: symbol 'ti81xx_rtc_hwmod' was not declared. Should it be static? Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Keerthy 提交于
pruss hwmod RSTST register wrongly points to PWRSTCTRL register in case of am43xx. Fix the RSTST register offset value. This can lead to setting of wrong power state values for PER domain. Fixes: 1c7e224d ("ARM: OMAP2+: hwmod: AM335x: runtime register update") Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 10 6月, 2016 12 次提交
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由 Tomi Valkeinen 提交于
The addresses for DSS are provided in the DT data, so they can be removed from the hwmod. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Vignesh R 提交于
QSPI address space information is passed from device tree. Therefore remove legacy way of passing address space via hwmod data. Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
The new pdata callback (force_ick_on) is now used by the driver and the old callback related code can be removed. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
McBSP2/3 module's sidetone module operates using the module's ICLK clock. When the Sidetone is in use the interface clock of the module must not idle. To prevent the iclk idling the driver expects to have pdata callback to call. With this patch the callback is going to be set up for DT boot also. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
McBSP2/3 module's sidetone module operates using the module's ICLK clock. When the Sidetone is in use the interface clock of the module must not idle. The new callback expects to receive the *clk of the module's ick and not the id number of the McBSP. This will allow us more cleanups and going to simplify the ICLK handling. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
The McBSPLP's sidetone main clock is the McBSPLP's ICLK, not FCLK as the sidetone only receives the ICLK from the main McBSP module. Since the McBSP and sidetone is using the very same clock from PRCM level the sidetone must not have the prcm section to check the clock status since the sidetone is only used when McBSP is already configured. If two separate hwmods looking at the same bit and they would use pm_runtime in nested way (as it must happen with McBSP and it's ST module) the hwmod would warn, because the idlest will not match what it is expected after enable/disable of the clocks. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Franklin S Cooper Jr 提交于
Devices that utilize the OCP registers and/or PRCM registers and register bit fields should be modeled using hwmod. Since eQEP, ePWM and eCAP don't fall under this category, remove their hwmod entries. Instead these clocks simply use the clock that is passed through by its parent PWMSS. Therefore, PWMSS handles the clock for itself and its subdevices. Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 03 6月, 2016 3 次提交
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由 Peter Ujfalusi 提交于
Instead of the full omapdss internal header, include only the platform_data header. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
The omap_display_init() is implemented in the mach-omap2/display.c so the declaration should have been there as well. Change the board files to include display.h to avoid build breakage at the same time. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
OMAP_DSS_VENC_TYPE_COMPOSITE is 0. There is no need to explicitly set the connector_type. This change is needed for the omapdss header cleanup. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: NTony Lindgren <tony@atomide.com>
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- 13 5月, 2016 1 次提交
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由 Nishanth Menon 提交于
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Based on ARM errata Document revision 18.0 (22 Nov 2013) Note: the configuration for the workaround needs to be done with each CPU bringup, since CPU0 bringup is done by bootloader, it is recommended to have the workaround in the bootloader, kernel also does ensure that CPU0 has the workaround and makes the workaround active when CPU1 gets active. With CONFIG_SMP disabled, it is expected to be done by the bootloader. This does show significant degradation in synthetic tests such as mbw (https://packages.qa.debian.org/m/mbw.html) mbw -n 100 100|grep AVG (on a test platform) Without enabling the erratum: AVG Method: MEMCPY Elapsed: 0.13406 MiB: 100.00000 Copy: 745.913 MiB/s AVG Method: DUMB Elapsed: 0.06746 MiB: 100.00000 Copy: 1482.357 MiB/s AVG Method: MCBLOCK Elapsed: 0.03058 MiB: 100.00000 Copy: 3270.569 MiB/s After enabling the erratum: AVG Method: MEMCPY Elapsed: 0.13757 MiB: 100.00000 Copy: 726.913 MiB/s AVG Method: DUMB Elapsed: 0.12024 MiB: 100.00000 Copy: 831.668 MiB/s AVG Method: MCBLOCK Elapsed: 0.09243 MiB: 100.00000 Copy: 1081.942 MiB/s Most benchmarks are designed for specific performance analysis, so overall usecase must be considered before making a decision to enable/disable the erratum workaround. Pending internal investigation, the erratum is kept disabled by default. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Tony Lindgren <tony@atomide.com> Suggested-by: NRichard Woodruff <r-woodruff2@ti.com> Suggested-by: NBrad Griffis <bgriffis@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 29 4月, 2016 2 次提交
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由 Tony Lindgren 提交于
Let's pass the slot names in pdata like the legacy code does. Once we have a generic DT binding for the slot names we can switch to that. Tested-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Before we start removing omap3 legacy booting support, let's make n900 DT booting behave the same way for ir-rx51 as the legacy booting does. For now, we need to pass pdata to the ir-rx51 driver. This means that the n900 tree can move to using DT based booting without having to carry all the legacy platform data with it when it gets dropped from the mainline tree. Note that the ir-rx51 driver is currently disabled because of the dependency to !ARCH_MULTIPLATFORM. This will get sorted out later with the help of drivers/pwm/pwm-omap-dmtimer.c. But first we need to add chained IRQ support to dmtimer code to avoid introducing new custom frameworks. So let's just pass the necessary dmtimer functions to ir-rx51 so we can get it working in the following patch. Cc: Neil Armstrong <narmstrong@baylibre.com> Tested-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 25 4月, 2016 1 次提交
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由 Viresh Kumar 提交于
The cpufreq-dt-platdev driver supports creation of cpufreq-dt platform device now, reuse that and remove similar code from platform code. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 19 4月, 2016 1 次提交
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由 Tony Lindgren 提交于
This reverts commit 571afb4c.
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- 15 4月, 2016 3 次提交
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由 Tony Lindgren 提交于
We can now just use the compatible if there's no need to have device instance specific auxdata. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
Move NAND specific device tree parsing to NAND driver. The NAND controller node must have a compatible id, register space resource and interrupt resource. Signed-off-by: NRoger Quadros <rogerq@ti.com> Acked-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com>
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由 Roger Quadros 提交于
Deprecate nand register passing via platform data and use gpmc_omap_get_nand_ops() instead. Signed-off-by: NRoger Quadros <rogerq@ti.com> Acked-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NTony Lindgren <tony@atomide.com>
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- 14 4月, 2016 2 次提交
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由 Dave Gerlach 提交于
Depending on timing during the resume path from off mode on 36xx, we may see external aborts. These seem to be caused by the following: - OMAP3 Advisory 1.62 "MPU Cannot Exit from Standby" says we need to disable intc autoidle before WFI - DM3730 Advisory 1.106 "MPU Leaves MSTANDBY State Before IDLEREQ of Interrupt Controller is Released" says we need to wait before accessing intc omap3_intc_resume_idle restores the intc autoidle for all resume paths, however in the resume path from off mode only it is also being restored by omap_intc_restore_context before this call to omap3_intc_resume_idle happens. The second restore of the intc autoidle in this path is what appears to be causing the external abort so for the off mode resume path let's rely on omap_intc_restore_context to restore intc autoidle, and for all other paths let omap3_intc_resume_idle handle it as it is now. Signed-off-by: NDave Gerlach <d-gerlach@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Anna-Maria Gleixner 提交于
FROZEN hotplug notifiers are not handled and do not have to be. Insert a comment to remember that the lack of the FROZEN transitions is no accident. Cc: Tony Lindgren <tony@atomide.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: linux-omap@vger.kernel.org Signed-off-by: NAnna-Maria Gleixner <anna-maria@linutronix.de> Acked-by: NSantosh Shilimkar <ssantosh@kernel.org> Signed-off-by: NTony Lindgren <tony@atomide.com>
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