- 09 6月, 2019 1 次提交
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由 Leo Yan 提交于
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel, so can dismiss warning during initialisation. Cc: Andy Gross <agross@kernel.org> Cc: David Brown <david.brown@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NLeo Yan <leo.yan@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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- 30 5月, 2019 2 次提交
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由 Amit Kucheria 提交于
Instead of using Qualcomm-specific terminology, use generic node names for the idle states that are easier to understand. Move the description into the "idle-state-name" property. Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org> Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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由 Amit Kucheria 提交于
The idle-states binding documentation[1] mentions that the 'entry-method' property is required on 64-bit platforms and must be set to "psci". [1] Documentation/devicetree/bindings/arm/idle-states.txt (see idle-states node) Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NNiklas Cassel <niklas.cassel@linaro.org> Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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- 24 4月, 2019 1 次提交
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由 Matthias Kaehlcke 提交于
Add 'xo_board' as ref clock for the DSI PHYs, it was previously hardcoded in the PLL 'driver' for the 28nm PHY. Signed-off-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NStephen Boyd <swboyd@chromium.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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- 10 4月, 2019 3 次提交
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由 Amit Kucheria 提交于
We don't have any cooling-devices related to the camera. Use the "hot" trip type so allow the temperature to be exported to userspace and remove the "critical" trip. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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由 Amit Kucheria 提交于
Maintain naming consistency with what was landed for sdm845. Simplifies parsing for test tools. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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由 Amit Kucheria 提交于
On platforms that have a modem, sensor 0 monitors the modem. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <agross@kernel.org>
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- 07 2月, 2019 1 次提交
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由 Niklas Cassel 提交于
The apcs node has #clock-cells = <0>, which means that those who references it should specify 0 arguments. The apcs reference in the cpu node incorrectly specifies an argument, remove this bogus argument. Fixes: 65afdf45 ("arm64: dts: qcom: msm8916: Add CPU frequency scaling support") Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 31 1月, 2019 1 次提交
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由 Rob Herring 提交于
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: NMichal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: NAntoine Tenart <antoine.tenart@bootlin.com> Acked-by: NNishanth Menon <nm@ti.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: NChanho Min <chanho.min@lge.com> Acked-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NGregory CLEMENT <gregory.clement@bootlin.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NTero Kristo <t-kristo@ti.com> Acked-by: NWei Xu <xuwei5@hisilicon.com> Acked-by: NLiviu Dudau <liviu.dudau@arm.com> Acked-by: NMatthias Brugger <matthias.bgg@gmail.com> Acked-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NScott Branden <scott.branden@broadcom.com> Acked-by: NKevin Hilman <khilman@baylibre.com> Acked-by: NChunyan Zhang <zhang.lyra@gmail.com> Acked-by: NRobert Richter <rrichter@cavium.com> Acked-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NDinh Nguyen <dinguyen@kernel.org> Signed-off-by: NRob Herring <robh@kernel.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 04 12月, 2018 3 次提交
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由 Todor Tomov 提交于
Add a node for the Camera Subsystem present on the Qualcomm MSM8916 SoC. Signed-off-by: NTodor Tomov <todor.tomov@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Todor Tomov 提交于
Add IOMMU sub-node for VFE secure context bank. Signed-off-by: NTodor Tomov <todor.tomov@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Viresh Kumar 提交于
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 15 11月, 2018 4 次提交
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由 Amit Kucheria 提交于
Initialise the camera thermal zone to export temperature to userspace. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Acked-by: NAndy Gross <andy.gross@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Amit Kucheria 提交于
Initialise the gpu thermal zone to export temperature to userspace. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Acked-by: NAndy Gross <andy.gross@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Amit Kucheria 提交于
This new property allows the number of sensors to be configured from DT instead of being hardcoded in platform data. Use it. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Acked-by: NAndy Gross <andy.gross@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Amit Kucheria 提交于
We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8916 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Acked-by: NAndy Gross <andy.gross@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 27 9月, 2018 1 次提交
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由 Suzuki K Poulose 提交于
Switch to updated coresight bindings for hw ports Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 14 9月, 2018 1 次提交
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由 Niklas Cassel 提交于
DTS board files should always specify model and compatible. All DTS board files that includes msm8916.dtsi already specifies model and compatible, and will thus override the model and compatible in msm8916.dtsi. Drop model and compatible from msm8916.dtsi, since they are only a source of confusion. Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 22 7月, 2018 1 次提交
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由 Niklas Cassel 提交于
Drop legacy suffix for clocks used by MSM DRM driver. The _clk suffix has been deprecated since commit 20c3bb80235 ("drm/msm: drop _clk suffix from clk names"). Fixes: 720c3bb8 (drm/msm: drop _clk suffix from clk names) The following warnings during boot have been seen since the referenced fixes commit: msm_dsi_phy 1a98300.dsi-phy: Using legacy clk name binding. Use "iface" instead of "iface_clk" msm 1a00000.mdss: Using legacy clk name binding. Use "iface" instead of "iface_clk" msm 1a00000.mdss: Using legacy clk name binding. Use "bus" instead of "bus_clk" msm 1a00000.mdss: Using legacy clk name binding. Use "vsync" instead of "vsync_clk" msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "bus" instead of "bus_clk" msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "iface" instead of "iface_clk" msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "core" instead of "core_clk" msm_mdp 1a01000.mdp: Using legacy clk name binding. Use "vsync" instead of "vsync_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "mdp_core" instead of "mdp_core_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "iface" instead of "iface_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "bus" instead of "bus_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "byte" instead of "byte_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "pixel" instead of "pixel_clk" msm_dsi 1a98000.dsi: Using legacy clk name binding. Use "core" instead of "core_clk" Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org> Reviewed-by: NNicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 23 6月, 2018 1 次提交
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由 Rob Herring 提交于
The ETF input should be connected to the funnel output, and the ETF output should be connected to the replicator input. The labels are wrong and these got swapped: Warning (graph_endpoint): /soc/funnel@821000/ports/port@8/endpoint: graph connection to node '/soc/etf@825000/ports/port@1/endpoint' is not bidirectional Warning (graph_endpoint): /soc/replicator@824000/ports/port@2/endpoint: graph connection to node '/soc/etf@825000/ports/port@0/endpoint' is not bidirectional Fixes: 7c10da37 ("arm64: dts: qcom: Add msm8916 CoreSight components") Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: linux-arm-msm@vger.kernel.org Signed-off-by: NRob Herring <robh@kernel.org> Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org> Tested-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 23 5月, 2018 1 次提交
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由 Srinivas Kandagatla 提交于
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from patch (83a86fbb "irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE"). Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: NThierry Escande <thierry.escande@linaro.org> Tested-by: NThierry Escande <thierry.escande@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 09 3月, 2018 5 次提交
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由 Rajendra Nayak 提交于
Add cpu cooling maps for cpu passive trip points. The cpu cooling device states are mapped to cpufreq based scaling frequencies. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Reviewed-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Georgi Djakov 提交于
Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Reviewed-by: NAmit Kucheria <amit.kucheria@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Georgi Djakov 提交于
There are clock controller registers in the APCS block, which purpose is to control the main CPU mux and divider. Add the clock properties as part of the APCS device-tree node. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Georgi Djakov 提交于
The APCS block was exposed until now as a syscon, but now we have a proper driver for this block. Add the compatible string of the new driver to probe and register the mailbox functionality. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Georgi Djakov 提交于
Add a device tree node for the A53 PLL, which exists on msm8916 platforms. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 01 1月, 2018 3 次提交
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由 Damien Riegel 提交于
The QUP core can be used either for I2C or SPI, so the same IP is mapped by a driver or the other. SPI bindings use a leading 0 for the start address and a size of 0x600, I2C bindings don't have the leading 0 and have a size 0x1000. To make them more similar, add the leading 0 to I2C bindings and changes the size to 0x500 for all of them, as this is the actual size of these blocks. Also align the second entry of the clocks array. Signed-off-by: NDamien Riegel <damien.riegel@savoirfairelinux.com> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Bjorn Andersson 提交于
SMSM is not symmetrical, the incoming bits from WCNSS are available at index 6, but the outgoing host id for WCNSS is 3. Further more, upstream references the base of APCS (in contrast to downstream), so the register offset of 8 must be included. Fixes: 1fb47e0a ("arm64: dts: qcom: msm8916: Add smsm and smp2p nodes") Cc: stable@vger.kernel.org Reported-by: NRamon Fried <rfried@codeaurora.org> Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Bjorn Andersson 提交于
Add a missing #phy-cells to the dsi-phy, to silence dtc warning. Cc: Archit Taneja <architt@codeaurora.org> Fixes: 305410ff ("arm64: dts: msm8916: Add display support") Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 20 10月, 2017 1 次提交
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由 Rob Herring 提交于
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*' Signed-off-by: NRob Herring <robh@kernel.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 12 10月, 2017 3 次提交
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由 Bjorn Andersson 提交于
Now that we have a binding defined for the shared file system memory use this to describe the rmtfs memory region. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Craig Tatlor 提交于
This shrinks the address size down to 89000 from its previous 90000 which was mistakenly pulled from downstream. Signed-off-by: NCraig Tatlor <ctatlor97@gmail.com> Acked-by: NRob Clark <robdclark@gmail.com> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Bjorn Andersson 提交于
On msm8916 and msm8996 boards a secure io-write is used to write the magic for selecting "download mode", specify this address in the DeviceTree. Note that qcom_scm.download_mode=1 must be specified on the kernel command line for the kernel to attempt selecting download mode. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 16 8月, 2017 3 次提交
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由 Rob Clark 提交于
This patch adds the IOMMU node for the IOMMU that resides on the Qualcomm MSM8916 platforms. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Stanimir Varbanov 提交于
This patch adds the Qualcomm Venus video codec node for the video codec hardware residing on MSM8916 platforms. Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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由 Rob Clark 提交于
This patch adds the Qualcomm Adreno GPU node that exists in the MSM8916. Signed-off-by: NRob Clark <robdclark@gmail.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 09 8月, 2017 1 次提交
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由 Suzuki K. Poulose 提交于
Replace the obsolete compatible string for Coresight programmable replicator with the new one. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: linux-arm-msm@vger.kernel.org Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 09 6月, 2017 1 次提交
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由 Leo Yan 提交于
Add debug unit on Qualcomm msm8916 based platforms, including the DragonBoard 410c board. Signed-off-by: NLeo Yan <leo.yan@linaro.org> Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org> Acked-by: NAndy Gross <andy.gross@linaro.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 26 5月, 2017 1 次提交
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由 Stephen Boyd 提交于
We currently have three device nodes for the same USB hardware block, as evident by the reuse of the same reg address multiple times. Now that the chipidea driver fully supports OTG with the MSM wrapper we can collapse all these nodes into one USB device node, reflecting the true nature of the hardware. Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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- 29 3月, 2017 1 次提交
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由 Bjorn Andersson 提交于
It's necessary to reference the xo clock and cx supply, so specify these in the node. Also move the Hexagon smd-edge into the hexagon node, to enable SSR. As cxo is not yet available we reference the fixed version of cxo for now, which will work until proper power management is implemented. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NAndy Gross <andy.gross@linaro.org>
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