1. 20 3月, 2018 1 次提交
  2. 19 12月, 2017 3 次提交
  3. 05 12月, 2017 1 次提交
  4. 02 12月, 2017 1 次提交
  5. 01 12月, 2017 1 次提交
  6. 14 11月, 2017 1 次提交
  7. 10 11月, 2017 1 次提交
    • V
      drm/i915: Nuke intel_digital_port->port · 8f4f2797
      Ville Syrjälä 提交于
      Remove intel_digital_port->port and replace its users with
      intel_encoder->port. intel_encoder->port is a superset of
      intel_digital_port->port, and it works correctly even for
      MST encoders.
      
      v2: Eliminate a few dp_to_dig_port()->base.port cases too (DK)
      
      Performed with cocci:
      @@
      @@
      struct intel_digital_port {
             ...
      -       enum port port;
             ...
      }
      
      @@
      struct intel_digital_port *D;
      expression E;
      @@
      - D->port = E;
      
      @@
      struct intel_digital_port *D;
      @@
      - D->port
      + D->base.port
      
      @
      expression E;
      @@
      (
      - dp_to_dig_port(E)->port
      + dp_to_dig_port(E)->base.port
      |
      - enc_to_dig_port(E)->port
      + to_intel_encoder(E)->port
      )
      
      @@
      expression E;
      @@
      - to_intel_encoder(&E->base)
      + E
      
      @@
      struct intel_digital_port *D;
      identifier I, M;
      @@
        I = &D->base
      <...
      (
      - D->base.M
      + I->M
      |
      - &D->base
      + I
      )
      ...>
      
      @@
      identifier D;
      expression E;
      identifier M;
      @@
       D = enc_to_dig_port(&E->base)
      <...
      (
      - D->base.M
      + E->M
      |
      - &D->base
      + E
      )
      ...>
      
      @@
      identifier D, DP;
      expression E;
      identifier M;
      @@
       DP = enc_to_intel_dp(&E->base)
      <...
      (
      - dp_to_dig_port(DP)->base.M
      + E->M
      |
      - &dp_to_dig_port(DP)->base
      + E
      )
      ...>
      
      @@
      expression E;
      identifier M;
      @@
      (
      - enc_to_dig_port(&E->base)->base.M
      + E->M
      |
      - enc_to_dig_port(&E->base)->base
      + E
      |
      - enc_to_mst(&E->base)->primary->base.port
      + E->port
      )
      
      @@
      expression E;
      identifier D;
      @@
      - struct intel_digital_port *D = E;
      ... when != D
      
      Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Reviewed-by: NDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Acked-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171109152434.32074-1-ville.syrjala@linux.intel.com
      8f4f2797
  8. 01 11月, 2017 1 次提交
  9. 31 10月, 2017 6 次提交
  10. 28 10月, 2017 1 次提交
  11. 27 10月, 2017 3 次提交
  12. 25 10月, 2017 2 次提交
    • V
      drm/i915: Adjust system agent voltage on CNL if required by DDI ports · 53e9bf5e
      Ville Syrjälä 提交于
      On CNL we may need to bump up the system agent voltage not only due
      to CDCLK but also when driving DDI port with a sufficiently high clock.
      To that end start tracking the minimum acceptable voltage for each crtc.
      We do the tracking via crtcs because we don't have any kind of encoder
      state. Also there's no downside to doing it this way, and it matches how
      we track cdclk requirements on account of pixel rate.
      
      v2: Allow disabled crtcs to use the min voltage
          Add IS_CNL check to intel_ddi_compute_min_voltage() since
          we're using CNL specific values there
          s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
          the function makes hw specific assumptions about the voltage
          values
      v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
      v4: s/voltage/voltage_level/ (Rodrigo)
          Replace DPLL DVFS FIXMEs with an explanation why we don't
          do anything there (Rodrigo)
      
      Cc: Mika Kahola <mika.kahola@intel.com>
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-9-ville.syrjala@linux.intel.com
      53e9bf5e
    • R
      drm/i915/cnl: Force DDI_A_4_LANES when needed. · 436009b5
      Rodrigo Vivi 提交于
      As we faced in BXT, on CNL DDI_A_4_LANES is not
      set as expected when system is boot with multiple
      monitors connected. This result in wrong lane
      setup impacting the max data rate available and
      consequently blocking modeset on eDP, resulting
      in a blank screen.
      
      Most of CNL SKUs don't support DDI-E.
      The only SKU that supports DDI-E is the same
      that supports the full A/E split called DDI-F.
      
      Also when DDI-F is used DDI-E cannot be used because
      they share Interrupts. So DDI-E is almost useless.
      Anyways let's consider this is possible and rely on
      VBT for that.
      
      This patch was initialy start by Clint, but required
      many changes including full commit message. So
      Credits entirely to Clint for finding this.
      
      v2: Extract all messy conditions into a helper function
          as suggested by Ville.
          Along with simplification I removed the debug
          message on the working case since now all conditions
          are grouped.
      v3: Split the conditions even more as suggested by Ville.
          Get's cleaner and easier to add new cases in the
          future.
      Suggested-by: NClint Taylor <clinton.a.taylor@intel.com>
      Cc: Clint Taylor <clinton.a.taylor@intel.com>
      Cc: Mika Kahola <mika.kahola@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171023173920.22890-1-rodrigo.vivi@intel.com
      436009b5
  13. 21 10月, 2017 1 次提交
  14. 19 10月, 2017 10 次提交
  15. 17 10月, 2017 3 次提交
  16. 14 10月, 2017 4 次提交