1. 08 2月, 2019 1 次提交
  2. 06 2月, 2019 1 次提交
    • B
      IB/mlx5: Do not use hw_access_flags for be and CPU data · bf3b4f06
      Bart Van Assche 提交于
      Avoid that sparse reports the following for the mlx5 driver:
      
      drivers/infiniband/hw/mlx5/qp.c:2671:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2671:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2671:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2679:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2679:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2679:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2680:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2680:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2680:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2684:34: warning: invalid assignment: |=
      drivers/infiniband/hw/mlx5/qp.c:2684:34:    left side has type restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2684:34:    right side has type int
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: incorrect type in argument 1 (different base types)
      drivers/infiniband/hw/mlx5/qp.c:2686:28:    expected unsigned int [usertype] val
      drivers/infiniband/hw/mlx5/qp.c:2686:28:    got restricted __be32 [usertype]
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      drivers/infiniband/hw/mlx5/qp.c:2686:28: warning: cast from restricted __be32
      
      This patch does not change any functionality.
      
      Fixes: a60109dc ("IB/mlx5: Add support for extended atomic operations")
      Signed-off-by: NBart Van Assche <bvanassche@acm.org>
      Acked-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      bf3b4f06
  3. 05 2月, 2019 1 次提交
  4. 22 1月, 2019 1 次提交
  5. 11 1月, 2019 1 次提交
  6. 03 1月, 2019 1 次提交
  7. 19 12月, 2018 2 次提交
  8. 15 12月, 2018 1 次提交
  9. 12 12月, 2018 1 次提交
  10. 08 12月, 2018 1 次提交
  11. 05 12月, 2018 1 次提交
  12. 30 11月, 2018 1 次提交
  13. 22 11月, 2018 3 次提交
  14. 17 10月, 2018 4 次提交
  15. 16 10月, 2018 1 次提交
  16. 04 10月, 2018 1 次提交
  17. 28 9月, 2018 1 次提交
  18. 27 9月, 2018 1 次提交
  19. 26 9月, 2018 8 次提交
  20. 22 9月, 2018 3 次提交
  21. 13 9月, 2018 1 次提交
  22. 07 9月, 2018 1 次提交
  23. 05 9月, 2018 1 次提交
    • M
      IB/mlx5: Change TX affinity assignment in RoCE LAG mode · c6a21c38
      Majd Dibbiny 提交于
      In the current code, the TX affinity is per RoCE device, which can cause
      unfairness between different contexts. e.g. if we open two contexts, and
      each open 10 QPs concurrently, all of the QPs of the first context might
      end up on the first port instead of distributed on the two ports as
      expected
      
      To overcome this unfairness between processes, we maintain per device TX
      affinity, and per process TX affinity.
      
      The allocation algorithm is as follow:
      
      1. Hold two tx_port_affinity atomic variables, one per RoCE device and one
         per ucontext. Both initialized to 0.
      
      2. In mlx5_ib_alloc_ucontext do:
       2.1. ucontext.tx_port_affinity = device.tx_port_affinity
       2.2. device.tx_port_affinity += 1
      
      3. In modify QP INIT2RST:
       3.1. qp.tx_port_affinity = ucontext.tx_port_affinity % MLX5_PORT_NUM
       3.2. ucontext.tx_port_affinity += 1
      Signed-off-by: NMajd Dibbiny <majd@mellanox.com>
      Reviewed-by: NMoni Shoua <monis@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      c6a21c38
  24. 15 8月, 2018 1 次提交
  25. 08 8月, 2018 1 次提交
    • L
      RDMA/mlx5: Fix shift overflow in mlx5_ib_create_wq · 0dfe4522
      Leon Romanovsky 提交于
      [   61.182439] UBSAN: Undefined behaviour in drivers/infiniband/hw/mlx5/qp.c:5366:34
      [   61.183673] shift exponent 4294967288 is too large for 32-bit type 'unsigned int'
      [   61.185530] CPU: 0 PID: 639 Comm: qp Not tainted 4.18.0-rc1-00037-g4aa1d69a9c60-dirty #96
      [   61.186981] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.10.2-2.fc27 04/01/2014
      [   61.188315] Call Trace:
      [   61.188661]  dump_stack+0xc7/0x13b
      [   61.190427]  ubsan_epilogue+0x9/0x49
      [   61.190899]  __ubsan_handle_shift_out_of_bounds+0x1ea/0x22f
      [   61.197040]  mlx5_ib_create_wq+0x1c99/0x1d50
      [   61.206632]  ib_uverbs_ex_create_wq+0x499/0x820
      [   61.213892]  ib_uverbs_write+0x77e/0xae0
      [   61.248018]  vfs_write+0x121/0x3b0
      [   61.249831]  ksys_write+0xa1/0x120
      [   61.254024]  do_syscall_64+0x7c/0x2a0
      [   61.256178]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
      [   61.259211] RIP: 0033:0x7f54bab70e99
      [   61.262125] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89
      [   61.268678] RSP: 002b:00007ffe1541c318 EFLAGS: 00000246 ORIG_RAX: 0000000000000001
      [   61.271076] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f54bab70e99
      [   61.273795] RDX: 0000000000000070 RSI: 0000000020000240 RDI: 0000000000000003
      [   61.276982] RBP: 00007ffe1541c330 R08: 00000000200078e0 R09: 0000000000000002
      [   61.280035] R10: 0000000000000000 R11: 0000000000000246 R12: 00000000004005c0
      [   61.283279] R13: 00007ffe1541c420 R14: 0000000000000000 R15: 0000000000000000
      
      Cc: <stable@vger.kernel.org> # 4.7
      Fixes: 79b20a6c ("IB/mlx5: Add receive Work Queue verbs")
      Cc: syzkaller <syzkaller@googlegroups.com>
      Reported-by: NNoa Osherovich <noaos@mellanox.com>
      Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
      0dfe4522