The datasheet said that emac register size is 0x10000 not 0x104
Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
[wens@csie.org: Fixed commit subject prefix]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

This reverts commits 2c0cba48 ("arm: sun8i: sunxi-h3-h5: Add dt node
for the syscon control module") to 2428fd0f ("arm64: defconfig: Enable
dwmac-sun8i driver on defconfig") and 3432a86e ("arm: sun8i:
orangepipc: use internal phy-mode") to 5a79b4f2 ("arm: sun8i:
orangepi-2: use internal phy-mode") that should be merged
through the arm-soc tree, and end up in merge conflicts and build failures.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
speed.

This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This patch add the dt node for the syscon register present on the
Allwinner H3/H5

Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock..
Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that the R_CCU device tree binding headers have been merged, we
can convert the raw number references in the device trees to use the
defined macros.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of
its parents.

This adds the reference in the device tree describing this relationship.
This patch uses a raw number for the clock index to ease merging by
avoiding cross tree dependencies.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
speed.

This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch add the dt node for the syscon register present on the
Allwinner H3/H5

Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock..
Signed-off-by: NCorentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The R_CCU of H3/H5 currently wrongly used A64 R_CCU compatible.

Fix it by changing it to the correct H3 compatible.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now we have driver for the PRCM CCU, switch to use it instead of
old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .

The mux 3 of R_CCU is still the internal oscillator, which is said to be
16MHz plus minus 30%, and get a measured value of 15MHz~16MHz on my two
H3 boards and one H5 board.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.

Add device nodes for these controllers.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
updated. So we should really share almost the whole .dtsi.
In preparation for that move the peripheral parts of the existing
sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi.
The actual sun8i-h3.dtsi then includes that and defines the H3 specific
parts on top of it.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
[Icenowy: also split out mmc and gic, as well as pio and ccu's
 compatible, and make drop of skeleton into a seperated patch]
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

According to the datasheets provided by Allwinner, both Allwinner H3 and
H5 use GIC-400 as their interrupt controller.

For better device tree reusing, correct the GIC compatible in H3 DTSI to
"arm,gic-400", thus this node can be reused in H5.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

After converting to generic pinconf binding, pinctrl-a10.h is now not
used at all.

Drop its inclusion for H3 DTSI.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The skeleton.dtsi file is now deprecated, and do not exist in ARM64
environment.

Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64
chip, drop skeleton.dtsi inclusion now.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the SPDIF transceiver controller block to the H3 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the SPDIF TX pin to the H3 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we support the audio codec found on the Allwinner H3 SoC, add
device nodes for it.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

In the past, all the MMC pins had

	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

which was actually a no-op. We were relying on U-boot to set the bias
pull up for us. These properties were removed as part of the fix up to
actually support no bias on the pins. During the transition some boards
experienced regular MMC time-outs during normal operation, while others
completely failed to initialize the SD card.

Given that MMC starts in open-drain mode and the pull-ups are required,
it's best to enable it for all the pin settings.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we can handle the generic pinctrl bindings, convert our DT to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

The allwinner,pull property set to NO_PULL was really considered our
default (and wasn't even changing the default value in the code).

Remove these properties to make it obvious that we do not set anything in
such a case.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

The allwinner,drive property set to 10mA was really considered as our
default. Remove all those properties entirely to make that obvious.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

In a previous commit, I made a copy/paste error in the pinmux
definitions of UART3: PG{13,14} instead of PA{13,14}. This commit takes
care of that. I have tested this commit on Orange Pi PC and Orange Pi
Plus, and it works for these boards.

Fixes: e3d11d3c ("dts: sun8i-h3: add pinmux definitions for
UART2-3")
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The pin controllers also use the two oscillators for debouncing. Add them
to the DTs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NChen-Yu Tsai <wens@csie.org>

H3 SPI subsystem is almost same as A31 SPI except buffer size, so those
DT properties are reusable.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: NMilo Kim <woogyom.kim@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are
configured through the pinctrl subsystem.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: NMilo Kim <woogyom.kim@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
and newer.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

These peripherals can only be muxed to these pins, so they are
associated in the DTSI instead of the board files. This makes it very
easy to enable them using overlays or u-boot commands:

 => fdt set /soc/i2c@01c2ac00 status okay
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

These are the only possible pins for these peripherals according to the
datasheet.
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This was done to make UART1-3 on H3 consistent, and less complicated to
enable UART1-3 on the breakout header on the several H3 board (notably
Orange Pi's). This patch adds a bit of complexity for the existing Banana
Pi, which already had the RTS/CTS associated on UART1.

The RTS/CTS for UART2-3 could be defined in the same way, but since
there is no actual use case for them at the moment, they are left out.
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

These are the pinmux definitions for UART2-3 on H3. These UARTs can only
be muxed to these pins, so _a and @0 do not really make sense. I have
left out RTS/CTS, since these are rarely used. These can easily be
enabled using an additional pinmux set.
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMilo Kim <woogyom.kim@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we have a different clock representation, switch to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-15-maxime.ripard@free-electrons.com

Add uart1 pins for 4 pin (RX/TX/RTS/CTS) mode.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Move uart0 pins to sort the list of pin settings in alphabetical order.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add nodes describing the H3's usbphy and usb host controller nodes.
Signed-off-by: NReinder de Haan <patchesrdh@mveas.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add a node describing the usb-clks found on the H3.
Signed-off-by: NReinder de Haan <patchesrdh@mveas.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add a pinctrl node for mmc2 in 8 bits mode on H3 SoCs.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The H3 ir receiver is completely compatible with the one found in the A31.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>