1. 20 5月, 2020 2 次提交
  2. 09 3月, 2020 3 次提交
  3. 17 1月, 2020 1 次提交
  4. 12 11月, 2019 1 次提交
  5. 24 9月, 2019 3 次提交
    • V
      KVM: x86: hyper-v: set NoNonArchitecturalCoreSharing CPUID bit when SMT is impossible · b2d8b167
      Vitaly Kuznetsov 提交于
      Hyper-V 2019 doesn't expose MD_CLEAR CPUID bit to guests when it cannot
      guarantee that two virtual processors won't end up running on sibling SMT
      threads without knowing about it. This is done as an optimization as in
      this case there is nothing the guest can do to protect itself against MDS
      and issuing additional flush requests is just pointless. On bare metal the
      topology is known, however, when Hyper-V is running nested (e.g. on top of
      KVM) it needs an additional piece of information: a confirmation that the
      exposed topology (wrt vCPU placement on different SMT threads) is
      trustworthy.
      
      NoNonArchitecturalCoreSharing (CPUID 0x40000004 EAX bit 18) is described in
      TLFS as follows: "Indicates that a virtual processor will never share a
      physical core with another virtual processor, except for virtual processors
      that are reported as sibling SMT threads." From KVM we can give such
      guarantee in two cases:
      - SMT is unsupported or forcefully disabled (just 'disabled' doesn't work
       as it can become re-enabled during the lifetime of the guest).
      - vCPUs are properly pinned so the scheduler won't put them on sibling
      SMT threads (when they're not reported as such).
      
      This patch reports NoNonArchitecturalCoreSharing bit in to userspace in the
      first case. The second case is outside of KVM's domain of responsibility
      (as vCPU pinning is actually done by someone who manages KVM's userspace -
      e.g. libvirt pinning QEMU threads).
      Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b2d8b167
    • V
      KVM/Hyper-V/VMX: Add direct tlb flush support · 6f6a657c
      Vitaly Kuznetsov 提交于
      Hyper-V provides direct tlb flush function which helps
      L1 Hypervisor to handle Hyper-V tlb flush request from
      L2 guest. Add the function support for VMX.
      Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com>
      Signed-off-by: NTianyu Lan <Tianyu.Lan@microsoft.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      6f6a657c
    • T
      x86/Hyper-V: Fix definition of struct hv_vp_assist_page · 7a83247e
      Tianyu Lan 提交于
      The struct hv_vp_assist_page was defined incorrectly.
      The "vtl_control" should be u64[3], "nested_enlightenments
      _control" should be a u64 and there are 7 reserved bytes
      following "enlighten_vmentry". Fix the definition.
      Signed-off-by: NTianyu Lan <Tianyu.Lan@microsoft.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7a83247e
  6. 22 7月, 2019 1 次提交
  7. 03 7月, 2019 1 次提交
    • M
      clocksource/drivers: Make Hyper-V clocksource ISA agnostic · fd1fea68
      Michael Kelley 提交于
      Hyper-V clock/timer code and data structures are currently mixed
      in with other code in the ISA independent drivers/hv directory as
      well as the ISA dependent Hyper-V code under arch/x86.
      
      Consolidate this code and data structures into a Hyper-V clocksource driver
      to better follow the Linux model. In doing so, separate out the ISA
      dependent portions so the new clocksource driver works for x86 and for the
      in-process Hyper-V on ARM64 code.
      
      To start, move the existing clockevents code to create the new clocksource
      driver. Update the VMbus driver to call initialization and cleanup routines
      since the Hyper-V synthetic timers are not independently enumerated in
      ACPI.
      
      No behavior is changed and no new functionality is added.
      Suggested-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NMichael Kelley <mikelley@microsoft.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NVitaly Kuznetsov <vkuznets@redhat.com>
      Cc: "bp@alien8.de" <bp@alien8.de>
      Cc: "will.deacon@arm.com" <will.deacon@arm.com>
      Cc: "catalin.marinas@arm.com" <catalin.marinas@arm.com>
      Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>
      Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>
      Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
      Cc: "linux-hyperv@vger.kernel.org" <linux-hyperv@vger.kernel.org>
      Cc: "olaf@aepfle.de" <olaf@aepfle.de>
      Cc: "apw@canonical.com" <apw@canonical.com>
      Cc: "jasowang@redhat.com" <jasowang@redhat.com>
      Cc: "marcelo.cerri@canonical.com" <marcelo.cerri@canonical.com>
      Cc: Sunil Muthuswamy <sunilmut@microsoft.com>
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: "sashal@kernel.org" <sashal@kernel.org>
      Cc: "vincenzo.frascino@arm.com" <vincenzo.frascino@arm.com>
      Cc: "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>
      Cc: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
      Cc: "linux-kselftest@vger.kernel.org" <linux-kselftest@vger.kernel.org>
      Cc: "arnd@arndb.de" <arnd@arndb.de>
      Cc: "linux@armlinux.org.uk" <linux@armlinux.org.uk>
      Cc: "ralf@linux-mips.org" <ralf@linux-mips.org>
      Cc: "paul.burton@mips.com" <paul.burton@mips.com>
      Cc: "daniel.lezcano@linaro.org" <daniel.lezcano@linaro.org>
      Cc: "salyzyn@android.com" <salyzyn@android.com>
      Cc: "pcc@google.com" <pcc@google.com>
      Cc: "shuah@kernel.org" <shuah@kernel.org>
      Cc: "0x7f454c46@gmail.com" <0x7f454c46@gmail.com>
      Cc: "linux@rasmusvillemoes.dk" <linux@rasmusvillemoes.dk>
      Cc: "huw@codeweavers.com" <huw@codeweavers.com>
      Cc: "sfr@canb.auug.org.au" <sfr@canb.auug.org.au>
      Cc: "pbonzini@redhat.com" <pbonzini@redhat.com>
      Cc: "rkrcmar@redhat.com" <rkrcmar@redhat.com>
      Cc: "kvm@vger.kernel.org" <kvm@vger.kernel.org>
      Link: https://lkml.kernel.org/r/1561955054-1838-2-git-send-email-mikelley@microsoft.com
      fd1fea68
  8. 15 5月, 2019 1 次提交
  9. 28 2月, 2019 1 次提交
  10. 21 12月, 2018 1 次提交
  11. 15 12月, 2018 5 次提交
  12. 09 10月, 2018 1 次提交
  13. 20 9月, 2018 1 次提交
  14. 06 8月, 2018 1 次提交
  15. 08 7月, 2018 1 次提交
  16. 03 7月, 2018 1 次提交
    • M
      Drivers: hv: vmbus: Make TLFS #define names architecture neutral · 7dc9b6b8
      Michael Kelley 提交于
      The Hyper-V feature and hint flags in hyperv-tlfs.h are all defined
      with the string "X64" in the name.  Some of these flags are indeed
      x86/x64 specific, but others are not.  For the ones that are used
      in architecture independent Hyper-V driver code, or will be used in
      the upcoming support for Hyper-V for ARM64, this patch removes the
      "X64" from the name.
      
      This patch changes the flags that are currently known to be
      used on multiple architectures. Hyper-V for ARM64 is still a
      work-in-progress and the Top Level Functional Spec (TLFS) has not
      been separated into x86/x64 and ARM64 areas.  So additional flags
      may need to be updated later.
      
      This patch only changes symbol names.  There are no functional
      changes.
      Signed-off-by: NMichael Kelley <mikelley@microsoft.com>
      Signed-off-by: NK. Y. Srinivasan <kys@microsoft.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      7dc9b6b8
  17. 26 5月, 2018 1 次提交
  18. 19 5月, 2018 2 次提交
  19. 15 5月, 2018 1 次提交
    • V
      KVM: x86: VMX: hyper-v: Enlightened MSR-Bitmap support · ceef7d10
      Vitaly Kuznetsov 提交于
      Enlightened MSR-Bitmap is a natural extension of Enlightened VMCS:
      Hyper-V Top Level Functional Specification states:
      
      "The L1 hypervisor may collaborate with the L0 hypervisor to make MSR
      accesses more efficient. It can enable enlightened MSR bitmaps by setting
      the corresponding field in the enlightened VMCS to 1. When enabled, the L0
      hypervisor does not monitor the MSR bitmaps for changes. Instead, the L1
      hypervisor must invalidate the corresponding clean field after making
      changes to one of the MSR bitmaps."
      
      I reached out to Hyper-V team for additional details and I got the
      following information:
      
      "Current Hyper-V implementation works as following:
      
      If the enlightened MSR bitmap is not enabled:
      - All MSR accesses of L2 guests cause physical VM-Exits
      
      If the enlightened MSR bitmap is enabled:
      - Physical VM-Exits for L2 accesses to certain MSRs (currently FS_BASE,
        GS_BASE and KERNEL_GS_BASE) are avoided, thus making these MSR accesses
        faster."
      
      I tested my series with a tight rdmsrl loop in L2, for KERNEL_GS_BASE the
      results are:
      
      Without Enlightened MSR-Bitmap: 1300 cycles/read
      With Enlightened MSR-Bitmap: 120 cycles/read
      Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com>
      Tested-by: NLan Tianyu <Tianyu.Lan@microsoft.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      ceef7d10
  20. 29 3月, 2018 6 次提交
  21. 17 3月, 2018 1 次提交
  22. 07 3月, 2018 2 次提交
    • M
      Drivers: hv: vmbus: Implement Direct Mode for stimer0 · 248e742a
      Michael Kelley 提交于
      The 2016 version of Hyper-V offers the option to operate the guest VM
      per-vcpu stimer's in Direct Mode, which means the timer interupts on its
      own vector rather than queueing a VMbus message. Direct Mode reduces
      timer processing overhead in both the hypervisor and the guest, and
      avoids having timer interrupts pollute the VMbus interrupt stream for
      the synthetic NIC and storage.  This patch enables Direct Mode by
      default on stimer0 when running on a version of Hyper-V that supports
      it.
      
      In prep for coming support of Hyper-V on ARM64, the arch independent
      portion of the code contains calls to routines that will be populated
      on ARM64 but are not needed and do nothing on x86.
      Signed-off-by: NMichael Kelley <mikelley@microsoft.com>
      Signed-off-by: NK. Y. Srinivasan <kys@microsoft.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      248e742a
    • R
      kvm: x86: hyperv: guest->host event signaling via eventfd · faeb7833
      Roman Kagan 提交于
      In Hyper-V, the fast guest->host notification mechanism is the
      SIGNAL_EVENT hypercall, with a single parameter of the connection ID to
      signal.
      
      Currently this hypercall incurs a user exit and requires the userspace
      to decode the parameters and trigger the notification of the potentially
      different I/O context.
      
      To avoid the costly user exit, process this hypercall and signal the
      corresponding eventfd in KVM, similar to ioeventfd.  The association
      between the connection id and the eventfd is established via the newly
      introduced KVM_HYPERV_EVENTFD ioctl, and maintained in an
      (srcu-protected) IDR.
      Signed-off-by: NRoman Kagan <rkagan@virtuozzo.com>
      Reviewed-by: NDavid Hildenbrand <david@redhat.com>
      [asm/hyperv.h changes approved by KY Srinivasan. - Radim]
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      faeb7833
  23. 20 2月, 2018 1 次提交
  24. 31 1月, 2018 1 次提交
    • V
      x86/hyperv: Reenlightenment notifications support · 93286261
      Vitaly Kuznetsov 提交于
      Hyper-V supports Live Migration notification. This is supposed to be used
      in conjunction with TSC emulation: when a VM is migrated to a host with
      different TSC frequency for some short period the host emulates the
      accesses to TSC and sends an interrupt to notify about the event. When the
      guest is done updating everything it can disable TSC emulation and
      everything will start working fast again.
      
      These notifications weren't required until now as Hyper-V guests are not
      supposed to use TSC as a clocksource: in Linux the TSC is even marked as
      unstable on boot. Guests normally use 'tsc page' clocksource and host
      updates its values on migrations automatically.
      
      Things change when with nested virtualization: even when the PV
      clocksources (kvm-clock or tsc page) are passed through to the nested
      guests the TSC frequency and frequency changes need to be know..
      
      Hyper-V Top Level Functional Specification (as of v5.0b) wrongly specifies
      EAX:BIT(12) of CPUID:0x40000009 as the feature identification bit. The
      right one to check is EAX:BIT(13) of CPUID:0x40000003. I was assured that
      the fix in on the way.
      Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: kvm@vger.kernel.org
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: "Michael Kelley (EOSG)" <Michael.H.Kelley@microsoft.com>
      Cc: Roman Kagan <rkagan@virtuozzo.com>
      Cc: Andy Lutomirski <luto@kernel.org>
      Cc: devel@linuxdriverproject.org
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: "K. Y. Srinivasan" <kys@microsoft.com>
      Cc: Cathy Avery <cavery@redhat.com>
      Cc: Mohammed Gamal <mmorsy@redhat.com>
      Link: https://lkml.kernel.org/r/20180124132337.30138-4-vkuznets@redhat.com
      93286261