1. 01 10月, 2020 1 次提交
    • J
      can: flexcan: initialize all flexcan memory for ECC function · a6597121
      Joakim Zhang 提交于
      One issue was reported at a baremetal environment, which is used for
      FPGA verification. "The first transfer will fail for extended ID
      format(for both 2.0B and FD format), following frames can be transmitted
      and received successfully for extended format, and standard format don't
      have this issue. This issue occurred randomly with high possiblity, when
      it occurs, the transmitter will detect a BIT1 error, the receiver a CRC
      error. According to the spec, a non-correctable error may cause this
      transfer failure."
      
      With FLEXCAN_QUIRK_DISABLE_MECR quirk, it supports correctable errors,
      disable non-correctable errors interrupt and freeze mode. Platform has
      ECC hardware support, but select this quirk, this issue may not come to
      light. Initialize all FlexCAN memory before accessing them, at least it
      can avoid non-correctable errors detected due to memory uninitialized.
      The internal region can't be initialized when the hardware doesn't support
      ECC.
      
      According to IMX8MPRM, Rev.C, 04/2020. There is a NOTE at the section
      11.8.3.13 Detection and correction of memory errors:
      "All FlexCAN memory must be initialized before starting its operation in
      order to have the parity bits in memory properly updated. CTRL2[WRMFRZ]
      grants write access to all memory positions that require initialization,
      ranging from 0x080 to 0xADF and from 0xF28 to 0xFFF when the CAN FD feature
      is enabled. The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers need to
      be initialized as well. MCR[RFEN] must not be set during memory initialization."
      
      Memory range from 0x080 to 0xADF, there are reserved memory (unimplemented
      by hardware, e.g. only configure 64 MBs), these memory can be initialized or not.
      In this patch, initialize all flexcan memory which includes reserved memory.
      
      In this patch, create FLEXCAN_QUIRK_SUPPORT_ECC for platforms which has ECC
      feature. If you have a ECC platform in your hand, please select this
      qurik to initialize all flexcan memory firstly, then you can select
      FLEXCAN_QUIRK_DISABLE_MECR to only enable correctable errors.
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Link: https://lore.kernel.org/r/20200929211557.14153-2-qiangqing.zhang@nxp.com
      [mkl: wrap long lines]
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      a6597121
  2. 22 9月, 2020 20 次提交
  3. 21 9月, 2020 1 次提交
  4. 08 12月, 2019 3 次提交
    • J
      can: flexcan: poll MCR_LPM_ACK instead of GPR ACK for stop mode acknowledgment · 048e3a34
      Joakim Zhang 提交于
      Stop Mode is entered when Stop Mode is requested at chip level and
      MCR[LPM_ACK] is asserted by the FlexCAN.
      
      Double check with IP owner, the MCR[LPM_ACK] bit should be polled for
      stop mode acknowledgment, not the acknowledgment from chip level which
      is used to gate flexcan clocks.
      
      This patch depends on:
      
          b7603d08 ("can: flexcan: add low power enter/exit acknowledgment helper")
      
      Fixes: 5f186c25 (can: flexcan: fix stop mode acknowledgment)
      Tested-by: NSean Nyekjaer <sean@geanix.com>
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Cc: linux-stable <stable@vger.kernel.org> # >= v5.0
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      048e3a34
    • J
      can: flexcan: add low power enter/exit acknowledgment helper · b7603d08
      Joakim Zhang 提交于
      The MCR[LPMACK] read-only bit indicates that FlexCAN is in a lower-power
      mode (Disabled mode, Doze mode, Stop mode).
      
      The CPU can poll this bit to know when FlexCAN has actually entered low
      power mode. The low power enter/exit acknowledgment helper will reduce
      code duplication for disabled mode, doze mode and stop mode.
      Tested-by: NSean Nyekjaer <sean@geanix.com>
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      b7603d08
    • S
      can: flexcan: fix possible deadlock and out-of-order reception after wakeup · e707180a
      Sean Nyekjaer 提交于
      When suspending, and there is still CAN traffic on the interfaces the
      flexcan immediately wakes the platform again. As it should :-). But it
      throws this error msg:
      
      [ 3169.378661] PM: noirq suspend of devices failed
      
      On the way down to suspend the interface that throws the error message
      calls flexcan_suspend() but fails to call flexcan_noirq_suspend(). That
      means flexcan_enter_stop_mode() is called, but on the way out of suspend
      the driver only calls flexcan_resume() and skips flexcan_noirq_resume(),
      thus it doesn't call flexcan_exit_stop_mode(). This leaves the flexcan
      in stop mode, and with the current driver it can't recover from this
      even with a soft reboot, it requires a hard reboot.
      
      This patch fixes the deadlock when using self wakeup, by calling
      flexcan_exit_stop_mode() from flexcan_resume() instead of
      flexcan_noirq_resume().
      
      This also fixes another issue: CAN frames are received out-of-order in
      first IRQ handler run after wakeup.
      
      The problem is that the wakeup latency from frame reception to the IRQ
      handler (where the CAN frames are sorted by timestamp) is much bigger
      than the time stamp counter wrap around time. This means it's
      impossible to sort the CAN frames by timestamp.
      
      The reason is that the controller exits stop mode during noirq resume,
      which means it receives frames immediately, but interrupt handling is
      still not possible.
      
      So exit stop mode during resume stage instead of noirq resume fixes this
      issue.
      
      Fixes: de3578c1 ("can: flexcan: add self wakeup support")
      Signed-off-by: NSean Nyekjaer <sean@geanix.com>
      Tested-by: NSean Nyekjaer <sean@geanix.com>
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Cc: linux-stable <stable@vger.kernel.org> # >= v5.0
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      e707180a
  5. 12 11月, 2019 12 次提交
    • M
      can: flexcan: flexcan_mailbox_read() make use of flexcan_write64() to mark the mailbox as read · b9468ad8
      Marc Kleine-Budde 提交于
      In the previous patch the function flexcan_write64() was introduced.
      
      This patch replaces the open coded variant in flexcan_mailbox_read()
      that marks a mailbox as read, by a single call to flexcan_write64().
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      b9468ad8
    • M
      can: flexcan: flexcan_irq(): add support for TX mailbox in iflag1 · b87c28b7
      Marc Kleine-Budde 提交于
      The flexcan IP core has up to 64 mailboxes, each one has a corresponding
      interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
      imask1 or imask2 registers.
      
      The driver will always use the last mailbox for TX, which falls into the iflag2
      register.
      
      To support CANFD the payload size has to increase to 64 bytes and the number of
      mailboxes will decrease so much that the TX mailbox will be handled in the
      iflag1 register.
      
      This patch add support to handle the TX mailbox independent whether it's
      in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx()
      function, similar to flexcan_read_reg_iflag_rx(), for the read path.
      
      For the write path the function flexcan_write64() is added.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      b87c28b7
    • M
      can: flexcan: flexcan_read_reg_iflag_rx(): optimize reading · d3a51507
      Marc Kleine-Budde 提交于
      The flexcan IP core has up to 64 mailboxes, each one has a corresponding
      interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
      imask1 or imask2 registers.
      
      In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX
      interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv
      for this.
      
      In certain use cases, for example the CANFD mode, the contents of the iflag2
      register is completely masked.
      
      This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading
      the iflag1 or iflag2 register if the contents is masked.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      d3a51507
    • M
      can: flexcan: introduce struct flexcan_priv::tx_mask and make use of it · 0ca64f02
      Marc Kleine-Budde 提交于
      The current driver uses FLEXCAN_IFLAG2_MB() to generate the mask to check for
      the TX complete interrupt. This works well, as the driver will always use the
      last mailbox for TX, which falls into the iflag2 register.
      
      To support CANFD the payload size has to increase to 64 bytes and the
      number of mailboxes will decrease so much that the TX mailbox will be
      handled in the iflag1 register.
      
      This patch introduces a tx_mask in the struct flexcan_priv (similar to rx_mask)
      and makes use of it. The actual support to handle the TX mailbox in iflag1 will
      be added in the next patches.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      0ca64f02
    • M
      can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to rx_mask · 8ce5139e
      Marc Kleine-Budde 提交于
      The flexcan IP core has up to 64 mailboxes, each one has a corresponding
      interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
      imask1 or imask2 registers.
      
      In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX
      interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of
      struct flexcan_priv for this.
      
      This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask
      variable, which simplifies the code a bit.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      8ce5139e
    • M
      can: flexcan: remove TX mailbox bit from struct flexcan_priv::rx_mask{1,2} · 9ed63c60
      Marc Kleine-Budde 提交于
      The flexcan IP core has up to 64 mailboxes, each one has a corresponding
      interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
      imask1 or imask2 registers.
      
      In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
      non RX interrupt sources and uses the precomputed values rx_mask1 and
      rx_mask2 of struct flexcan_priv for this.
      
      Currently these values cannot be used directly, as they contain the TX
      mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1
      and flexcan_priv::rx_mask2, and sets the TX flag directly when writing
      the regs->iflag1 and regs->iflag2 into the hardware.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      9ed63c60
    • M
      can: flexcan: rename struct flexcan_priv::reg_imask{1,2}_default to rx_mask{1,2} · 07c054d3
      Marc Kleine-Budde 提交于
      The flexcan IP core has up to 64 mailboxes, each one has a corresponding
      interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
      imask1 or imask2 registers.
      
      In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
      non RX interrupt sources and uses the precomputed values
      reg_imask1_default and reg_imask2_default of struct flexcan_priv for
      this.
      
      However in the current driver the reg_imask{1,2}_default cannot be used
      directly to get the pending RX interrupts. The TX interrupt is part of
      these variables, so it needs to be masked out, too.
      
      This is a preparation patch to clean up calculation of the pending RX
      interrupts, it only renames the variables from
      
          reg_imask{1,2}_default
      
      to
      
          rx_mask{1,2}
      
      To better reflect their meaning after the complete conversion. This
      change is done with the following sed command:
      
          sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      07c054d3
    • M
      can: flexcan: flexcan_irq(): rename variable reg_iflag -> reg_iflag_rx · 4e26598a
      Marc Kleine-Budde 提交于
      This patch renames the variable reg_iflag in the flexcan_irq() function
      to reg_iflag_rx. This better reflects the contents of the varibale. It
      does not hold the unmodified iflag registers, instead all non RX
      interrupts have been masked.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      4e26598a
    • M
      can: flexcan: rename macro FLEXCAN_IFLAG_MB() -> FLEXCAN_IFLAG2_MB() · b36d3c0f
      Marc Kleine-Budde 提交于
      The macro FLEXCAN_IFLAG_MB() is always used for the iflag2 register, so
      rename it to FLEXCAN_IFLAG2_MB()
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      b36d3c0f
    • M
      can: flexcan: flexcan_irq_state(): only read timestamp if needed · 58ed8e77
      Marc Kleine-Budde 提交于
      The function flexcan_irq_state() checks the controller for CAN state
      changes and pushes a skb with the new state and a timestamp into the
      rx-offload framework.
      
      This patch optimizes the function by only reading the timestamp, if a
      state change is detected.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      58ed8e77
    • J
      can: flexcan: use devm_platform_ioremap_resource() to simplify code · a4721f27
      Joakim Zhang 提交于
      Use the new helper devm_platform_ioremap_resource() which wraps the
      platform_get_resource() and devm_ioremap_resource() together to simplify
      the code.
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Reviewed-by: NSean Nyekjaer <sean@geanix.com>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      a4721f27
    • J
      can: rx-offload: Prepare for CAN FD support · 4e9c9484
      Joakim Zhang 提交于
      The skbs for classic CAN and CAN FD frames are allocated with seperate
      functions: alloc_can_skb() and alloc_canfd_skb().
      
      In order to support CAN FD frames via the rx-offload helper, the driver
      itself has to allocate the skb (depending whether it received a classic
      CAN or CAN FD frame), as the rx-offload helper cannot know which kind of
      CAN frame the driver has received.
      
      This patch moves the allocation of the skb into the struct
      can_rx_offload::mailbox_read callbacks of the the flexcan and ti_hecc
      driver and adjusts the rx-offload helper accordingly.
      Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      4e9c9484
  6. 05 11月, 2019 2 次提交
  7. 24 7月, 2019 1 次提交