- 01 10月, 2020 1 次提交
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由 Joakim Zhang 提交于
One issue was reported at a baremetal environment, which is used for FPGA verification. "The first transfer will fail for extended ID format(for both 2.0B and FD format), following frames can be transmitted and received successfully for extended format, and standard format don't have this issue. This issue occurred randomly with high possiblity, when it occurs, the transmitter will detect a BIT1 error, the receiver a CRC error. According to the spec, a non-correctable error may cause this transfer failure." With FLEXCAN_QUIRK_DISABLE_MECR quirk, it supports correctable errors, disable non-correctable errors interrupt and freeze mode. Platform has ECC hardware support, but select this quirk, this issue may not come to light. Initialize all FlexCAN memory before accessing them, at least it can avoid non-correctable errors detected due to memory uninitialized. The internal region can't be initialized when the hardware doesn't support ECC. According to IMX8MPRM, Rev.C, 04/2020. There is a NOTE at the section 11.8.3.13 Detection and correction of memory errors: "All FlexCAN memory must be initialized before starting its operation in order to have the parity bits in memory properly updated. CTRL2[WRMFRZ] grants write access to all memory positions that require initialization, ranging from 0x080 to 0xADF and from 0xF28 to 0xFFF when the CAN FD feature is enabled. The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers need to be initialized as well. MCR[RFEN] must not be set during memory initialization." Memory range from 0x080 to 0xADF, there are reserved memory (unimplemented by hardware, e.g. only configure 64 MBs), these memory can be initialized or not. In this patch, initialize all flexcan memory which includes reserved memory. In this patch, create FLEXCAN_QUIRK_SUPPORT_ECC for platforms which has ECC feature. If you have a ECC platform in your hand, please select this qurik to initialize all flexcan memory firstly, then you can select FLEXCAN_QUIRK_DISABLE_MECR to only enable correctable errors. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20200929211557.14153-2-qiangqing.zhang@nxp.com [mkl: wrap long lines] Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 22 9月, 2020 20 次提交
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由 Joakim Zhang 提交于
The Flexcan on lx2160ar1 supports CAN FD protocol. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-9-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
The Flexcan on i.MX8QM supports CAN FD protocol. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-8-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
The CAN-FD protocol allows the transmission and reception of data at a higher bit rate than the nominal rate used in the arbitration phase when the message's BRS bit is set. The TDC mechanism is effective only during the data phase of FD frames having BRS bit set. It has no effect either on non-FD frames, or on FD frames transmitted at normal bit rate. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-7-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
This patch adds CAN FD BitRate Switch (BRS) support to driver. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-5-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
ISO CAN FD is introduced to increase the failture detection capability than non-ISO CAN FD. The non-ISO CAN FD is still supported by FlexCAN so that it can be used mainly during an intermediate phase, for evaluation and development purposes. Therefore, it is strongly recommended to configure FlexCAN to the ISO CAN FD protocol by setting the ISOCANFDEN field in the CTRL2 register. NOTE: If you only set "fd on", driver will use ISO FD mode by default. You should set "fd-non-iso on" after setting "fd on" if you want to use NON ISO FD mode. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-6-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
This patch adds CAN-FD mode support to the driver, it means that payload size can extend up to 64 bytes. Bit timing always set in the CBT register, not in the CTRL1 register any more. This has an extend range of all CAN bit timing variables (PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW), which will improve the bit timing accuracy. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> [mkl: move cbt-based bitrate support into separate function] Link: https://lore.kernel.org/r/20200922144429.2613631-16-mkl@pengutronix.deSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
This patch prepares for CAN FD mode, using struct canfd_frame can both for classic format frame and fd format frame. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20190712075926.7357-3-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
This is a patch prepares for the CAN-FD support. In a later patch the setup for canfd bittiming will be added, with this patch the change is easier to read. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-14-mkl@pengutronix.de
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由 Joakim Zhang 提交于
On the i.MX7D in LPSR mode, the controller will be powered off and the configuration state is lost after system resume. Upcoming i.MX8QM/QXP will also completely power off the domain, the controller state is lost and needs restore, too. So we need to set the pinctrl state again and re-start chip to re-configuration after resume. For the wakeup case, it should not set pinctrl to sleep state by pinctrl_pm_select_sleep_state. If the interface is down before suspend, we don't need to re-configure it as it will be configured if the interface is brought up later. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20191204113249.3381-7-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
Disable clocks while CAN core is in stop mode. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Tested-by: NSean Nyekjaer <sean@geanix.com> Link: https://lore.kernel.org/r/20191210085721.9853-2-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
This patch implements error handling and propagates the error value of flexcan_chip_stop(). This function will be called from flexcan_suspend() in an upcoming patch in some SoCs which support LPSR mode. Add a new function flexcan_chip_stop_disable_on_error() that tries to disable the chip even in case of errors. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> [mkl: introduce flexcan_chip_stop_disable_on_error() and use it in flexcan_close()] Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-11-mkl@pengutronix.de
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由 Joakim Zhang 提交于
commit cdce8448 ("can: flexcan: add vf610 support for FlexCAN") From above commit by Stefan Agner, the patch just disables non-correctable errors interrupt and freeze mode. It still can correct the correctable errors since ECC enabled by default after reset (MECR[ECCDIS]=0, enable memory error correct) if HW supports ECC. commit 5e269324 ("can: flexcan: disable completely the ECC mechanism") From above commit by Joakim Zhang, the patch disables ECC completely (assert MECR[ECCDIS]) according to the explanation of FLEXCAN_QUIRK_DISABLE_MECR that disable memory error detection. This cause correctable errors cannot be corrected even HW supports ECC. The error correction mechanism ensures that in this 13-bit word, errors in one bit can be corrected (correctable errors) and errors in two bits can be detected but not corrected (non-correctable errors). Errors in more than two bits may not be detected. If HW supports ECC, we can use this to correct the correctable errors detected from FlexCAN memory. Then disable non-correctable errors interrupt and freeze mode to avoid that put FlexCAN in freeze mode. This patch adds correctable errors correction when HW supports ECC, and modify explanation for FLEXCAN_QUIRK_DISABLE_MECR. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20200416093126.15242-1-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
CAN FD can transmit up to 8Mbps, but some transceivers only can support 5Mbps, so add check in driver. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20191030064245.12923-2-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
As the transcevier regulator is optional, this patch switches from devm_regulator_get() to devm_regulator_get_optional(). This gets rid of "using dummy regulator" warning message from the regulator core, if no regulator is available. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-8-mkl@pengutronix.de
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由 Joakim Zhang 提交于
As FLEXCAN_ESR_ALL_INT is for all bus errors and state change IRQ sources, strictly speaking FLEXCAN_ESR_WAK_INT does not belong to these. So add wakeup interrupt ack separately to existing ack of the interrupts. Suggested-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Link: https://lore.kernel.org/r/20191204113249.3381-3-qiangqing.zhang@nxp.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
This patch reformats the quirks to get rid of long lines. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-6-mkl@pengutronix.de
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由 Marc Kleine-Budde 提交于
This patch documents which registers are not affected by a soft reset of the flexcan IP core. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-5-mkl@pengutronix.de
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由 Marc Kleine-Budde 提交于
This patch adds some new register names and tries to ensure with a static_assert that the documented offset is correct. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-4-mkl@pengutronix.de
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由 Marc Kleine-Budde 提交于
This patch removes a stray empty line from the flexcan_exit_stop_mode() function. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-3-mkl@pengutronix.de
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由 Marc Kleine-Budde 提交于
This patch sorts the include files alphabetically. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20200922144429.2613631-2-mkl@pengutronix.de
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- 21 9月, 2020 1 次提交
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由 Alexandre Belloni 提交于
Fix a mistake in a register layout description. Signed-off-by: NAlexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200214141751.21168-1-alexandre.belloni@bootlin.comSigned-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 08 12月, 2019 3 次提交
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由 Joakim Zhang 提交于
Stop Mode is entered when Stop Mode is requested at chip level and MCR[LPM_ACK] is asserted by the FlexCAN. Double check with IP owner, the MCR[LPM_ACK] bit should be polled for stop mode acknowledgment, not the acknowledgment from chip level which is used to gate flexcan clocks. This patch depends on: b7603d08 ("can: flexcan: add low power enter/exit acknowledgment helper") Fixes: 5f186c25 (can: flexcan: fix stop mode acknowledgment) Tested-by: NSean Nyekjaer <sean@geanix.com> Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Cc: linux-stable <stable@vger.kernel.org> # >= v5.0 Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
The MCR[LPMACK] read-only bit indicates that FlexCAN is in a lower-power mode (Disabled mode, Doze mode, Stop mode). The CPU can poll this bit to know when FlexCAN has actually entered low power mode. The low power enter/exit acknowledgment helper will reduce code duplication for disabled mode, doze mode and stop mode. Tested-by: NSean Nyekjaer <sean@geanix.com> Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Sean Nyekjaer 提交于
When suspending, and there is still CAN traffic on the interfaces the flexcan immediately wakes the platform again. As it should :-). But it throws this error msg: [ 3169.378661] PM: noirq suspend of devices failed On the way down to suspend the interface that throws the error message calls flexcan_suspend() but fails to call flexcan_noirq_suspend(). That means flexcan_enter_stop_mode() is called, but on the way out of suspend the driver only calls flexcan_resume() and skips flexcan_noirq_resume(), thus it doesn't call flexcan_exit_stop_mode(). This leaves the flexcan in stop mode, and with the current driver it can't recover from this even with a soft reboot, it requires a hard reboot. This patch fixes the deadlock when using self wakeup, by calling flexcan_exit_stop_mode() from flexcan_resume() instead of flexcan_noirq_resume(). This also fixes another issue: CAN frames are received out-of-order in first IRQ handler run after wakeup. The problem is that the wakeup latency from frame reception to the IRQ handler (where the CAN frames are sorted by timestamp) is much bigger than the time stamp counter wrap around time. This means it's impossible to sort the CAN frames by timestamp. The reason is that the controller exits stop mode during noirq resume, which means it receives frames immediately, but interrupt handling is still not possible. So exit stop mode during resume stage instead of noirq resume fixes this issue. Fixes: de3578c1 ("can: flexcan: add self wakeup support") Signed-off-by: NSean Nyekjaer <sean@geanix.com> Tested-by: NSean Nyekjaer <sean@geanix.com> Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Cc: linux-stable <stable@vger.kernel.org> # >= v5.0 Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 12 11月, 2019 12 次提交
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由 Marc Kleine-Budde 提交于
In the previous patch the function flexcan_write64() was introduced. This patch replaces the open coded variant in flexcan_mailbox_read() that marks a mailbox as read, by a single call to flexcan_write64(). Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. The driver will always use the last mailbox for TX, which falls into the iflag2 register. To support CANFD the payload size has to increase to 64 bytes and the number of mailboxes will decrease so much that the TX mailbox will be handled in the iflag1 register. This patch add support to handle the TX mailbox independent whether it's in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx() function, similar to flexcan_read_reg_iflag_rx(), for the read path. For the write path the function flexcan_write64() is added. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv for this. In certain use cases, for example the CANFD mode, the contents of the iflag2 register is completely masked. This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading the iflag1 or iflag2 register if the contents is masked. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The current driver uses FLEXCAN_IFLAG2_MB() to generate the mask to check for the TX complete interrupt. This works well, as the driver will always use the last mailbox for TX, which falls into the iflag2 register. To support CANFD the payload size has to increase to 64 bytes and the number of mailboxes will decrease so much that the TX mailbox will be handled in the iflag1 register. This patch introduces a tx_mask in the struct flexcan_priv (similar to rx_mask) and makes use of it. The actual support to handle the TX mailbox in iflag1 will be added in the next patches. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of struct flexcan_priv for this. This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask variable, which simplifies the code a bit. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of struct flexcan_priv for this. Currently these values cannot be used directly, as they contain the TX mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1 and flexcan_priv::rx_mask2, and sets the TX flag directly when writing the regs->iflag1 and regs->iflag2 into the hardware. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX interrupt sources and uses the precomputed values reg_imask1_default and reg_imask2_default of struct flexcan_priv for this. However in the current driver the reg_imask{1,2}_default cannot be used directly to get the pending RX interrupts. The TX interrupt is part of these variables, so it needs to be masked out, too. This is a preparation patch to clean up calculation of the pending RX interrupts, it only renames the variables from reg_imask{1,2}_default to rx_mask{1,2} To better reflect their meaning after the complete conversion. This change is done with the following sed command: sed -i -e "s/reg_imask\(1\|2\)_default/rx_mask\1/" drivers/net/can/flexcan.c Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
This patch renames the variable reg_iflag in the flexcan_irq() function to reg_iflag_rx. This better reflects the contents of the varibale. It does not hold the unmodified iflag registers, instead all non RX interrupts have been masked. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The macro FLEXCAN_IFLAG_MB() is always used for the iflag2 register, so rename it to FLEXCAN_IFLAG2_MB() Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Marc Kleine-Budde 提交于
The function flexcan_irq_state() checks the controller for CAN state changes and pushes a skb with the new state and a timestamp into the rx-offload framework. This patch optimizes the function by only reading the timestamp, if a state change is detected. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together to simplify the code. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Reviewed-by: NSean Nyekjaer <sean@geanix.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
The skbs for classic CAN and CAN FD frames are allocated with seperate functions: alloc_can_skb() and alloc_canfd_skb(). In order to support CAN FD frames via the rx-offload helper, the driver itself has to allocate the skb (depending whether it received a classic CAN or CAN FD frame), as the rx-offload helper cannot know which kind of CAN frame the driver has received. This patch moves the allocation of the skb into the struct can_rx_offload::mailbox_read callbacks of the the flexcan and ti_hecc driver and adjusts the rx-offload helper accordingly. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 05 11月, 2019 2 次提交
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由 Marc Kleine-Budde 提交于
The call to can_rx_offload_queue_sorted() may fail and return an error (in the current implementation due to resource shortage). The passed skb is consumed. This patch adds incrementing of the appropriate error counters to let the device statistics reflect that there's a problem. Reported-by: NMartin Hundebøll <martin@geanix.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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由 Joakim Zhang 提交于
The ECC (memory error detection and correction) mechanism can be activated or not, controlled by the ECCDIS bit in CAN_MECR. When disabled, updates on indications and reporting registers are stopped. So if want to disable ECC completely, had better assert ECCDIS bit, not just mask the related interrupts. Fixes: cdce8448 ("can: flexcan: add vf610 support for FlexCAN") Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 24 7月, 2019 1 次提交
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由 Joakim Zhang 提交于
To enter stop mode, the CPU should manually assert a global Stop Mode request and check the acknowledgment asserted by FlexCAN. The CPU must only consider the FlexCAN in stop mode when both request and acknowledgment conditions are satisfied. Fixes: de3578c1 ("can: flexcan: add self wakeup support") Reported-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Cc: linux-stable <stable@vger.kernel.org> # >= v5.0 Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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