1. 28 1月, 2019 1 次提交
    • Y
      spi: spi-mem: Add driver for NXP FlexSPI controller · a5356aef
      Yogesh Narayan Gaur 提交于
      - Add driver for NXP FlexSPI host controller
      
      (0) What is the FlexSPI controller?
       FlexSPI is a flexsible SPI host controller which supports two SPI
       channels and up to 4 external devices. Each channel supports
       Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
       data lines) i.e. FlexSPI acts as an interface to external devices,
       maximum 4, each with up to 8 bidirectional data lines.
      
       It uses new SPI memory interface of the SPI framework to issue
       flash memory operations to up to four connected flash
       devices (2 buses with 2 CS each).
      
      (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
       on NXP LX2160ARDB and LX2160AQDS targets.
       LX2160ARDB is having two NOR slave device connected on single bus A
       i.e. A0 and A1 (CS0 and CS1).
       LX2160AQDS is having two NOR slave device connected on separate buses
       one flash on A0 and second on B1 i.e. (CS0 and CS3).
       Verified this driver on following SPI NOR flashes:
          Micron, mt35xu512ab, [Read - 1 bit mode]
          Cypress, s25fl512s, [Read - 1/2/4 bit mode]
      Signed-off-by: NYogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
      Reviewed-by: NFrieder Schrempf <frieder.schrempf@kontron.de>
      Reviewed-by: NBoris Brezillon <bbrezillon@kernel.org>
      Tested-by: NAshish Kumar <Ashish.Kumar@nxp.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      a5356aef
  2. 17 1月, 2019 2 次提交
    • A
      spi: ath79: Enable support for compile test · b172fd0c
      Alban Bedel 提交于
      To allow building this driver in compile test we need to remove all
      dependency on headers from arch/mips/include. To allow this we
      explicitly define all the registers locally instead of using
      ar71xx_regs.h and we move the platform data struct definition to
      include/linux/platform_data/spi-ath79.h.
      Signed-off-by: NAlban Bedel <albeu@free.fr>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      b172fd0c
    • A
      spi: ath79: Simplify ath79_spi_chipselect() · 797622d7
      Alban Bedel 提交于
      First of all this callback was slightly misused to setup the clock
      polarity at the beginning of a transfer. Beside being at the wrong
      place, it is also useless as only SPI mode 1 is supported. Instead
      just make sure the base value used for IOC is suitable to start a
      transfer by clearing the clock and data bits during the controller
      setup.
      
      This also remove the last direct usage of the GPIO API, so we can
      remove the direct dependency on GPIOLIB.
      Signed-off-by: NAlban Bedel <albeu@free.fr>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      797622d7
  3. 08 1月, 2019 3 次提交
  4. 11 12月, 2018 1 次提交
  5. 14 11月, 2018 1 次提交
  6. 07 11月, 2018 2 次提交
  7. 05 11月, 2018 1 次提交
  8. 21 10月, 2018 1 次提交
  9. 19 10月, 2018 1 次提交
    • L
      spi: spi-mem: add stm32 qspi controller · c530cd1d
      Ludovic Barre 提交于
      The qspi controller is a specialized communication interface
      targeting single, dual or quad SPI Flash memories (NOR/NAND).
      
      It can operate in any of the following modes:
      -indirect mode: all the operations are performed using the quadspi
       registers
      -read memory-mapped mode: the external Flash memory is mapped to the
       microcontroller address space and is seen by the system as if it was
       an internal memory
      
      tested on:
      -NOR: mx66l51235l
      -NAND: MT29F2G01ABAGD
      Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      c530cd1d
  10. 11 10月, 2018 2 次提交
  11. 28 9月, 2018 1 次提交
  12. 10 9月, 2018 1 次提交
  13. 29 8月, 2018 1 次提交
  14. 01 8月, 2018 1 次提交
  15. 31 5月, 2018 1 次提交
  16. 11 5月, 2018 1 次提交
  17. 10 5月, 2018 1 次提交
  18. 18 4月, 2018 1 次提交
  19. 26 3月, 2018 2 次提交
  20. 12 2月, 2018 1 次提交
  21. 03 11月, 2017 1 次提交
  22. 06 10月, 2017 1 次提交
    • A
      spi: spreadtrum adi: add hwspinlock dependency · e83f3742
      Arnd Bergmann 提交于
      With CONFIG_HWSPINLOCK=m, the new driver fails to link as a built-in driver:
      
      drivers/spi/spi-sprd-adi.o: In function `sprd_adi_remove':
      spi-sprd-adi.c:(.text+0x18): undefined reference to `hwspin_lock_free'
      drivers/spi/spi-sprd-adi.o: In function `sprd_adi_probe':
      spi-sprd-adi.c:(.text+0xfc): undefined reference to `of_hwspin_lock_get_id'
      spi-sprd-adi.c:(.text+0x108): undefined reference to `hwspin_lock_request_specific'
      spi-sprd-adi.c:(.text+0x268): undefined reference to `hwspin_lock_free'
      
      This adds a hard Kconfig dependency on HWSPINLOCK for the !COMPILE_TEST
      case, and allows compile-testing with HWSPINLOCK completely disabled,
      which will then rely on the existing stub API.
      
      Fixes: 7e2903cb ("spi: Add ADI driver for Spreadtrum platform")
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      e83f3742
  23. 20 9月, 2017 1 次提交
  24. 19 9月, 2017 1 次提交
  25. 16 8月, 2017 1 次提交
    • L
      spi: altera: Switch to SPI core transfer queue management · e19b63cd
      Lars-Peter Clausen 提交于
      The Altera SPI driver currently uses the spi-bitbang infrastructure for
      transfer queue management, but non of the bitbang functionality itself.
      This is because when the driver was written this was the only way to not
      have to do queue management in the driver itself.
      
      Nowadays transfer queue management is available from the SPI driver core
      itself and using the bitbang infrastructure just adds an additional level
      of indirection.
      
      Switch the driver over to using the core queue management directly.
      Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      e19b63cd
  26. 07 8月, 2017 1 次提交
    • A
      spi: fix building SPI_PXA on MMP · 128345b1
      Arnd Bergmann 提交于
      When the audio driver selects CONFIG_PXA_SSP on ARCH_MMP as a
      loadable module, and the PXA SPI driver is built-in, we get
      a link error in the SPI driver:
      
      drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_remove':
      spi-pxa2xx.c:(.text+0x5f0): undefined reference to `pxa_ssp_free'
      drivers/spi/spi-pxa2xx.o: In function `pxa2xx_spi_probe':
      spi-pxa2xx.c:(.text+0xeac): undefined reference to `pxa_ssp_request'
      spi-pxa2xx.c:(.text+0x1468): undefined reference to `pxa_ssp_free'
      spi-pxa2xx.c:(.text+0x15bc): undefined reference to `pxa_ssp_free'
      
      The problem is that the PXA SPI driver only uses 'select SSP'
      specifically when building it for PXA, but we can also build it
      for PCI, which is meant for Intel x86 SoCs that use the same SPI
      block. When the sound driver forces the SSP to be a loadable
      module, the IS_ENABLED() check in include/linux/pxa2xx_ssp.h
      triggers but the spi driver can't reference the exported symbols.
      
      I had a different approach before, making the PCI case depend
      on X86, which fixed the problem by avoiding the MMP case.
      
      This goes a different route, making the driver select PXA_SSP
      also on MMP, which has an SSP that none of the boards in mainline
      Linux use for SPI. There is no harm in always enabling the build
      on MMP (PCI or not PCI), so I do that too, to document that this
      hardware is actually available on MMP.
      
      Link: https://patchwork.kernel.org/patch/8879921/Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      128345b1
  27. 21 6月, 2017 1 次提交
  28. 26 5月, 2017 3 次提交
  29. 25 5月, 2017 1 次提交
  30. 14 5月, 2017 1 次提交
  31. 14 3月, 2017 1 次提交
  32. 20 2月, 2017 1 次提交