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  1. 22 9月, 2009 1 次提交
  3. 18 9月, 2009 2 次提交
  5. 17 9月, 2009 5 次提交
  7. 15 9月, 2009 1 次提交
  9. 14 9月, 2009 1 次提交
  11. 12 9月, 2009 1 次提交
    • J
      ASoC: Clean up error handling in MPC5200 DMA setup · 33d7f778
      由 Julia Lawall 提交于 
      Error handling code following a kzalloc should free the allocated data.
Error handling code following an ioremap should iounmap the allocated data.

The semantic match that finds the first problem is as follows:
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@r exists@
local idexpression x;
statement S;
expression E;
identifier f,f1,l;
position p1,p2;
expression *ptr != NULL;
@@

x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
...
if (x == NULL) S
<... when != x
     when != if (...) { <+...x...+> }
(
x->f1 = E
|
 (x->f1 == NULL || ...)
|
 f(...,x->f1,...)
)
...>
(
 return \(0\|<+...x...+>\|ptr\);
|
 return@p2 ...;
)

@script:python@
p1 << r.p1;
p2 << r.p2;
@@

print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
// </smpl>
Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      33d7f778
  13. 09 9月, 2009 1 次提交
    • M
      ASoC: au1x: PSC-AC97 bugfixes · cdc65fbe
      由 Manuel Lauss 提交于 
      This patch fixes the following bugs:

- only reprogram bitdepth if it has changed since last call to hw_params.
- add locking inside ac97_read/write functions:
  When reprogramming sample depth, the ac97 unit has to be disabled,
  which should not be done in the middle of codec register accesses.

- retry timed-out codec register accesses.

- wait for status bits to set/clear when starting/stopping various
  functional blocks; very important after reenabling AC97 unit else
  sound may be distorted (e.g. high-pitch noise in 1kHz sine wave).

- clear fifos before/after starting/stopping RX/TX.

- longer timeouts waiting for PSC/AC97 ready after cold reset
  with certain codecs this can take ridiculous amounts of time.

Run-tested on various Au1200 platforms with various codecs.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      cdc65fbe
  15. 08 9月, 2009 1 次提交
  17. 05 9月, 2009 1 次提交
  19. 03 9月, 2009 1 次提交
  21. 01 9月, 2009 2 次提交
  23. 29 8月, 2009 1 次提交
    • J
      ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI · d2c0bdaa
      由 Jarkko Nikula 提交于 
      The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have
specifications to check it) have additional CLKR and FSR pins for McBSP1
receiver. Reset default is that receiver is using bit clock and frame
sync signal from those pins but it is possible to configure to use
also CLKX and FSX pins as well. In fact, other McBSP ports are doing that
internally that transmitter and receiver share the CLKX and FSX.

Add functionaly that machine drivers can set the CLKR and FSR sources by
using the snd_soc_dai_set_sysclk.

Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue.
Signed-off-by: NJarkko Nikula <jhnikula@gmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      d2c0bdaa
  25. 28 8月, 2009 1 次提交
  27. 26 8月, 2009 5 次提交
  29. 25 8月, 2009 4 次提交
    • S
      ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time · faf907c7
      由 Shine Liu 提交于 
      s3c24xx dma has the auto reload feature, when the the trnasfer is done,
CURR_TC(DSTAT[19:0], current value of transfer count) reaches 0, and DMA
ACK becomes 1, and then, TC(DCON[19:0]) will be loaded into CURR_TC. So
the transmission is repeated.

IRQ is issued while auto reload occurs. We change the DISRC and
DCON[19:0] in the ISR, but at this time, the auto reload has been
performed already. The first block is being re-transmitted by the DMA.

So we need rewrite the DISRC and DCON[19:0] for the next block
immediatly after the this block has been started to be transported.

The function s3c2410_dma_started() is for this perpose, which is called
in the form of "s3c2410_dma_ctrl(prtd->params->channel,
S3C2410_DMAOP_STARTED);" in s3c24xx_pcm_trigger().

But it is not correct. DMA transmission won't start until DMA REQ signal
arrived, it is the time s3c24xx_snd_txctrl(1) or s3c24xx_snd_rxctrl(1)
is called in s3c24xx_i2s_trigger().

In the current framework, s3c24xx_pcm_trigger() is always called before
s3c24xx_pcm_trigger(). So the s3c2410_dma_started() should be called in
s3c24xx_pcm_trigger() after s3c24xx_snd_txctrl(1) or
s3c24xx_snd_rxctrl(1) is called in this function.

However, s3c2410_dma_started() is dma related, to call this function we
should provide the channel number, which is given by
substream->runtime->private_data->params->channel. The private_data
points to a struct s3c24xx_runtime_data object, which is define in
s3c24xx_pcm.c, so s3c2410_dma_started() can't be called in s3c24xx_i2s.c

Fix this by moving the call to signal the DMA started to the DAI
drivers.
Signed-off-by: NShine Liu <liuxian@redflag-linux.com>
Signed-off-by: NShine Liu <shinel@foxmail.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      faf907c7
    • J
      ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop · d09a2afc
      由 Jarkko Nikula 提交于 
      Functionality of functions omap_mcbsp_xmit_enable and omap_mcbsp_recv_enable
can be merged into omap_mcbsp_start and omap_mcbsp_stop since API of
those omap_mcbsp_start and omap_mcbsp_stop was changed recently allowing
to start and stop individually the transmitter and receiver.

This cleans up the code in arch/arm/plat-omap/mcbsp.c and in
sound/soc/omap/omap-mcbsp.c which was the only user for those removed
functions.
Signed-off-by: NJarkko Nikula <jhnikula@gmail.com>
Acked-by: NEero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      d09a2afc
    • J
      ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI · 32080af7
      由 Jarkko Nikula 提交于 
      Commit ca6e2ce0 is setting up few XCCR and
RCCR bits for I2S and DPS_A formats. Part of the bits are already set
for all formats and I believe that XDISABLE and RDISABLE bits are
format independent.

As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup
of XDISABLE and RDISABLE to where those cpu's are tested and remove format
dependent part for simplicity.
Signed-off-by: NJarkko Nikula <jhnikula@gmail.com>
Acked-by: NEero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      32080af7
    • M
      ASoC: Select core DMA when building for S3C64xx · 239a22aa
      由 Mark Brown 提交于 
      Ensure that the core DMA support is available when building for
S3C64xx.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      239a22aa
  31. 24 8月, 2009 3 次提交
  33. 23 8月, 2009 1 次提交
  35. 22 8月, 2009 1 次提交
    • M
      ASoC: Add DAPM widget power decision debugfs files · 79fb9387
      由 Mark Brown 提交于 
      Currently when built with DEBUG DAPM will dump information about
the power state decisions it is taking for each widget to dmesg.
This isn't an ideal way of getting the information - it requires
a kernel build to turn it on and off and for large hub CODECs the
volume of information is so large as to be illegible. When the
output goes to the console it can also cause a noticable impact
on performance simply to print it out.

Improve the situation by adding a dapm directory to our debugfs
tree containing a file per widget with the same information in
it. This still requires a decision to build with debugfs support
but is easier to navigate and much less intrusive.

In addition to the previously displayed information active streams
are also shown in these files.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      79fb9387
  37. 21 8月, 2009 7 次提交