When CPU topology is specified in device tree, cpu_logical_map() does
not return core ID anymore, but rather full MPIDR value. This breaks
existing calculation of PMU register offsets on Exynos SoCs.

This patch fixes the problem by adjusting the code to use only core ID
bits of the value returned by cpu_logical_map() to allow CPU topology to
be specified in device tree on Exynos SoCs.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This solves a problem with building with CONFIG_SMP=n due to missing
sysram_base_addr (or sysram_ns_base_addr) variables.

The new setup method is more awkward than I'd like for it to be, but
it can't be done in init_early() since ioremap is not yet available,
but it needs to happen before SMP.
Reported-by: NRussell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Exynos5800 is an octa core SoC which is based on the 5420
platform. This patch adds the basic support for it in the
mach-exynos.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

A look at the code reveals use of S5P_VA_SYSRAM macro, in case of certain SoC
revisions, which is not valid any longer, after SYSRAM started to be mapped
dynamically. The new dynamic mapping is stored in sysram_base_addr variable,
which is declared static in platsmp.c

This fix makes sysram_base_addr non-static, declared it in common.h and used
in pm.c instead of S5P_VA_SYSRAM.
Suggested-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos specific macros and declarations have been moved to
mach-exynos. Inclusion of plat/cpu.h is no more necessary.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Use generic exynos cpu power control functions to power up/down
and to know the status of the cpu in platsmp and hotplug code.
Signed-off-by: NLeela Krishna Amudala <leela.krishna@linaro.org>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Instead of hardcoding the SYSRAM details for each SoC,
pass this information through device tree (DT) and make
the code SoC agnostic. Generic DT SRAM bindings are
used for achieving this.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This is a dummy placeholder file. Delete it.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This moves regs-pmu.h file into mach-exynos directory.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

We have a handy macro to replace open coded __cpuc_flush_dcache_area(()
and outer_clean_range() sequences. Let's use it. No functional change.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit  -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings.  In any case, they are temporary and harmless.

This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code.  It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>

The location at which the boot address is specified for secondary
CPUs of EXYNOS5420 is SYSRAM base + 4. Update the cpu_boot_reg
function accordingly.
Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Instead of having to specify the number for CPUs in EXYNOS5250 in
platsmp.c file, let the number of CPUs be determined by having this
information listed in EXYNOS5250 device tree file.
Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch reads the cpuid part number and if it matches with
cortex-A9, calls scu_enable()
Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Boards using secure firmware must use different CPU boot registers and
call secure firmware to boot the CPU.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NSrinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Tested-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NNicolas Pitre <nico@linaro.org>
Tested-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Barry Song <baohua.song@csr.com>

Now that we have GIC moved to drivers/irqchip and all GIC DT init for
platforms using irqchip_init, move gic.h and update the remaining
includes.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Samuel Ortiz <sameo@linux.intel.com>

In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos4412 uses different information register for each core. This
patch adjusts the bring-up code to take that into account.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Almost each SMP platform defines pen_release to manage booting secondary
CPUs. This of course clashes with the single zImage effort.

Add the pen_release definition to the ARM SMP code, and remove all others.
This should only be used by platforms which lack any kind of CPU power
management...
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Convert Exynos4 to use struct smp_operations to provide its SMP
and CPU hotplug operations.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NNicolas Pitre <nico@linaro.org>
Tested-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The EXYNOS5250 has two Cortex-A15 cores and there's no
need to call scu_enable() in platform_smp_prepare_cpus()
because Cortex-A15 has no regarding scu register which
can be used for getting number of cores.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

It turns out that the logical CPU mapping is useful even when !CONFIG_SMP
for manipulation of devices like interrupt and power controllers when
running a UP kernel on a CPU other than 0. This can happen when kexecing
a UP image from an SMP kernel.

In the future, multi-cluster systems running AMP configurations will
require something similar for mapping cluster IDs, so it makes sense to
decouple this logic in preparation for this support.
Acked-by: NYang Bai <hamo.by@gmail.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Reported-by: NJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

BSYM macro is only needed for assembly files and its usage in c files is
wrong, so remove it. The linker will correctly set bit 0 for Thumb2
kernels.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Dave Martin <dave.martin@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>

The GIC support code is heavily using the fact that hardware
implementations are exposing banked registers. Unfortunately, it
looks like at least one GIC implementation (EXYNOS) offers both
the distributor and the CPU interfaces at different addresses,
depending on the CPU.

This problem is solved by allowing the distributor and CPU interface
addresses to be per-cpu variables for the platforms that require it.
The EXYNOS code is updated not to mess with the GIC internals while
handling interrupts, and struct gic_chip_data is back to being private.
The DT binding for the gic is updated to allow an optional "cpu-offset"
value, which is used to compute the various base addresses.

Finally, a new config option (GIC_NON_BANKED) is used to control this
feature, so the overhead is only present on kernels compiled with
support for EXYNOS.

Tested on Origen (EXYNOS4) and Panda (OMAP4).

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has
made for plaforms based on EXYNOS4 SoCs. But since upcoming
Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most
codes in current mach-exynos4, one mach-exynos directory will
be used for them.

This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos)
but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to
avoid changing in driver side.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This reverts commit 4bd0fe1c.

This implementation can introduce a problem and 'ARM: SMP: fix
per cpu timer setup before the cpu is marked online' patch can
solve the cpu_oneline vs. cpu_active problem so that should be
reverted.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than clipping the number of CPUs using the compile-time NR_CPUS
constant, use the runtime nr_cpu_ids value instead.  This allows the
nr_cpus command line option to work as expected.

Cc: <stable@kernel.org>
Reported-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch uses the new cpu_logical_map() macro for converting logical
CPU numbers into physical numbers when dealing with the pen_release
variable in the SMP boot and CPU hotplug paths.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Tested-and-acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>

This patch adds two functions for gic interrupt handling.
1. Add interrupt handling of 4 cores.
2. Dynamically set gic bank offset according to the type of soc.
   Gic bank offset of EXYNOS4412 is 0x4000 while the offset of
   EXYNOS4210 and EXYNOS4212 is 0x8000.

This patch is necessary because EXYNOS4 socs cannot support
GIC register banking as described in commit aab74d3e.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The commit 5dfc54e0
("ARM: GIC: avoid routing interrupts to offline CPUs")
prevents routing interrupts to offline CPUs. But in
case of timer on EXYNOS4, the irq_set_affinity() method
is called in percpu_timer_setup() before CPU1 becomes
online. So this patch fixes routing timer interrupt to
offline CPU.
Reported-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch uses samsung_rev() to support variable silicon revision of
EXYNOS4210 so that can support for EXYNOS4210 REV0, REV1.0 and REV1.1.

Note: Need to change timer setting on REV0.
Acked-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

To insert the code for power on/off with pmu control to support hotplug in/out core1
As for hotplug.c, the codes for core1 to be hotplug in/out is inserted.
As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined.
As for platsmp.c, the codes for core1 to be powered on is inserted.
Signed-off-by: NJungHi Min <junghi.min@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

For full support of power modes, this patch adds implementation
external GIC on EXYNOS4.

External GIC of Exynos4 cannot support register banking so
several interrupt related code for CPU1 should be different
from that of CPU0.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

If an ARM system has multiple cpus in the same socket and the
kernel is booted with maxcpus=1, secondary cpus are possible but
not present due to how platform_smp_prepare_cpus() is called.
Since most typical ARM processors don't actually support physical
hotplug, initialize the present map to be equal to the possible
map in generic ARM SMP code. Also, always call
platform_smp_prepare_cpus() as long as max_cpus is non-zero (0
means no SMP) to allow platform code to do any SMP setup.

After applying this patch it's possible to boot an ARM system
with maxcpus=1 on the command line and then hotplug in secondary
cpus via sysfs. This is more in line with how x86 does things.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than having each platform class provide a mach/smp.h header for
smp_cross_call(), arrange for them to register the function with the
core ARM SMP code instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds EXYNOS4 CPU support files in mach-exynos4,
and basically they are moved from mach-s5pv310 so that it
can support Samsung's new CPU name, EXYNOS4.
The EXYNOS4 ingegrates a ARM Cortex A9 multi-core.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>