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  1. 11 5月, 2011 9 次提交
  3. 31 3月, 2011 1 次提交
  5. 23 3月, 2011 1 次提交
  7. 18 3月, 2011 2 次提交
    • M
      OMAP: DSS2: Implement OMAP4 DSS fclk support · 2de11086
      由 Murthy, Raghuveer 提交于 
      Add dss.dpll4_m4_ck (DSS FCLK) initialization for OMAP4. This is used
to compute the pixel clock for DPI interface and also to reconfigure
the DSS FCLK to the desired rate, corresponding to the rate computed
for pixel clock.

Adding these cpu_is_44xx() checks are meant to be temporary, until a
cleaner implementation to manage these checks are added. Currently this
is needed to get DVI display running on OMAP4 PandaBoard
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
[tomi.valkeinen@ti.com: minor changes due to conflicts]
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      2de11086
    • T
      OMAP: DSS2: Clean up for dpll4_m4_ck handling · 0acf659f
      由 Tomi Valkeinen 提交于 
      OMAP2 does not have dpll4_m4_ck source clock for dss functional clock,
but later OMAPs do. Currently we check for cpu type in multiple places
to find out if dpll4_m4_ck is available.

This patch cleans up dss.c by using the fact that dss.dpll4_m4_ck
pointer is NULL on OMAP2. This allows us to remove many of the cpu
checks.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      0acf659f
  9. 16 3月, 2011 8 次提交
  11. 15 3月, 2011 9 次提交
  13. 14 3月, 2011 1 次提交
  15. 11 3月, 2011 9 次提交
    • T
      OMAP4: DSS2: Clock source changes for OMAP4 · ea75159e
      由 Taneja, Archit 提交于 
      On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:

Lcd Pixel clock = DISPC_FCLK / lcd / pcd

Where lcd and pcd are divisors in the DISPC_DIVISOR register.

On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:

Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2

Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.

LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
and DSI2 PLL as clock sources respectively. Introduce functions to select and
get the clock source for these new clocks. Modify DISPC functions get the
correct lck and pck rates based on the clock source of these clocks. Since
OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
as DSS_CLK_SRC_FCK by introducing a dss feature.

Introduce clock source names for OMAP4 and some register field changes in
DSS_CTRL on OMAP4.

Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
clock.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ea75159e
    • T
      OMAP2PLUS: DSS2: Cleanup clock source related code · 66534e8e
      由 Taneja, Archit 提交于 
      Clean up some of the DSS functions which select/get clock sources, use switch
to select the clock source members since more clock sources will be introduced
later on.

Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy
inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity.
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      66534e8e
    • S
      OMAP: DSS2: Add support for LG Philips LB035Q02 panel · 7654b4d3
      由 Steve Sakoman 提交于 
      This patch adds support for the Gumstix Palo35 expansion board
which utilizes the 320 x 240 pixel LG.Philips LB035Q02 LCD Panel
Signed-off-by: NSteve Sakoman <steve@sakoman.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      7654b4d3
    • T
      OMAP: DSS2: fix omap_dispc_register_isr() fail path · b9cb0984
      由 Tomi Valkeinen 提交于 
      Fix handling of error in omap_dispc_register_isr() in case there are no
free isr slots available.
Reported-by: NBen Tucker <btucker@mpcdata.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      b9cb0984
    • M
      OMAP4: DSS2: Using dss_features to set independent core clock divider · 0cf35df3
      由 Murthy, Raghuveer 提交于 
      Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group

-----------------------------------------------------------------------
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:

	DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)

Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi

Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions
------------------------------------------------------------------------
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      0cf35df3
    • M
      OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch) · ce7fa5eb
      由 Murthy, Raghuveer 提交于 
      The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.

Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.

Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured

OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ce7fa5eb
    • M
      OMAP: DSS2: Adding dss_features for independent core clk divider · 5c6366e1
      由 Murthy, Raghuveer 提交于 
      In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.

In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.

The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      5c6366e1
    • T
      HACK: OMAP: DSS2: add delay after enabling clocks · 85604b0a
      由 Tomi Valkeinen 提交于 
      On omap4 the registers may not be accessible right after enabling the
clocks. At some point this will be handled by pm_runtime, but, for the
time begin, adding a small delay after clk_enable() should make things
work.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      85604b0a
    • T
      HACK: OMAP: DSS2: Fix OMAP2_DSS_USE_DSI_PLL · f2988ab9
      由 Tomi Valkeinen 提交于 
      When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock
for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator
changes broke this, causing the the code to not acquire the regulator
when using OMAP2_DSS_USE_DSI_PLL.

This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the
issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL
option working. There shouldn't be any other downside in this solution
than some extra lines of code.

OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and
the feature itself should be implemented in a more sane way. However,
the solution is not trivial, and people are using DSI PLL to get more
exact pixel clocks, so this hack is an acceptable temporary solution for
the time being.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      f2988ab9