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  1. 21 1月, 2015 1 次提交
  3. 18 1月, 2015 1 次提交
  5. 14 10月, 2014 1 次提交
  7. 06 10月, 2014 1 次提交
  9. 01 10月, 2014 1 次提交
    • R
      clk: add pxa clocks infrastructure · bda00303
      由 Robert Jarzmik 提交于 
      Add a the common code used by all PXA variants.

This is the first step in the transition from architecture defined
clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to
have the same features (and not all the features) of the existing
clocks, and enable the transition of PXA to device-tree.

All PXA rely on a "CKEN" type clock, which :
 - has a gate (bit in CKEN register)
 - is generated from a PLL, generally divided
 - has an alternate low power clock

Each variant will specialize the CKEN clock :
 - pxa25x have no low power clock
 - pxa27x in low power use always the 13 MHz ring oscillator
 - pxa3xx in low power have specific dividers for each clock

The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get
a handle on the clock. While pxa-clock.h will describe all the clocks of
all the variants, each variant will only use a subset of it.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      bda00303
  11. 27 9月, 2014 1 次提交
  13. 10 9月, 2014 2 次提交
  15. 29 7月, 2014 1 次提交
  17. 26 7月, 2014 1 次提交
  19. 02 7月, 2014 1 次提交
    • P
      clk: Add driver for Palmas clk32kg and clk32kgaudio clocks · 942d1d67
      由 Peter Ujfalusi 提交于 
      Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual device the provided clocks can be:
CLK32K_KG and CLK32K_KGAUDIO
or only one:
CLK32K_KG (TPS659039 for example)

Use separate compatible flags for the two 32K clock.
A system which needs or have only one of the 32k clock from
Palmas will need to add node(s) for each clock as separate section
in the dts file.
The two compatible property is:
"ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock

Apart from the register control of the clocks - which is done via
the clock API there is a posibility to enable the external sleep
control. In this way the clock can be enabled/disabled on demand by the
user of the clock.

See the documentation for more details.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      942d1d67
  21. 30 5月, 2014 1 次提交
  23. 23 5月, 2014 1 次提交
  25. 20 5月, 2014 1 次提交
  27. 15 5月, 2014 1 次提交
  29. 12 5月, 2014 1 次提交
  31. 26 3月, 2014 1 次提交
  33. 19 3月, 2014 2 次提交
  35. 25 2月, 2014 1 次提交
    • A
      clk: bcm281xx: add initial clock framework support · 1f27f152
      由 Alex Elder 提交于 
      Add code for device tree support of clocks in the BCM281xx family of
SoCs.  Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs).  (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)

A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC.  A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers.  There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more).  There are also "fractional" dividers which allow
division by non-integer values.  To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.

If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed.  The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.

The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock.  Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate.  (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)

The source code is divided into three general portions:

    drivers/clk/bcm/clk-kona.h
    drivers/clk/bcm/clk-kona.c
        These implement the basic Kona clock functionality,
        including the clk_ops methods and various routines to
        manipulate registers and interpret their values.  This
        includes some functions used to set clocks to a desired
        initial state (though this feature is only partially
        implemented here).

    drivers/clk/bcm/clk-kona-setup.c
        This contains generic run-time initialization code for
        data structures representing Kona CCUs and clocks.  This
        encapsulates the clock structure initialization that can't
        be done statically.  Note that there is a great deal of
        validity-checking code here, making explicit certain
        assumptions in the code.   This is mostly useful for adding
        new clock definitions and could possibly be disabled for
        production use.

    drivers/clk/bcm/clk-bcm281xx.c
        This file defines the specific CCUs used by BCM281XX family
        SoCs, as well as the specific clocks implemented by each.
        It declares a device tree clock match entry for each CCU
        defined.

    include/dt-bindings/clock/bcm281xx.h
        This file defines the selector (index) values used to
        identify a particular clock provided by a CCU.  It consists
        entirely of C preprocessor constants, to be used by both the
        C source and device tree source files.
Signed-off-by: NAlex Elder <elder@linaro.org>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMatt Porter <mporter@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>
      1f27f152
  37. 28 1月, 2014 1 次提交
  39. 18 1月, 2014 1 次提交
  41. 17 1月, 2014 2 次提交
  43. 15 12月, 2013 1 次提交
  45. 13 12月, 2013 1 次提交
  47. 04 12月, 2013 1 次提交
  49. 02 12月, 2013 1 次提交
    • B
      clk: at91: add PMC base support · 0ad6125b
      由 Boris BREZILLON 提交于 
      This patch adds at91 PMC (Power Management Controller) base support.

All at91 clocks managed by the PMC unit will use this framework.

This framework provides the following fonctionalities:
- define a new struct at91_pmc to hide PMC internals (lock, PMC memory
  mapping, irq domain, ...)
- read/write helper functions (pmc_read/write) to access PMC registers
- lock/unlock helper functions (pmc_lock/unlock) to lock/unlock access to
  pmc registers
- a new irq domain and its associated irq chip to request PMC specific
  interrupts (useful for clk prepare callbacks)

The PMC unit is declared as a dt clk provider (CLK_OF_DECLARE), and every
clk using this framework will declare a table of of_at91_clk_init_cb_t
and add it to the pmc_clk_ids table.

When the pmc dt clock setup function is called (by of_clk_init function),
it triggers the registration of every supported child clk (those matching
the definitions in pmc_clk_ids).

This patch copies at91_pmc_base (memory mapping) and at91sam9_idle
(function) from arch/arm/mach-at91/clock.c (which is not compiled if
COMMON_CLK_AT91 is enabled).
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      0ad6125b
  51. 05 11月, 2013 1 次提交
  53. 08 10月, 2013 2 次提交
  55. 09 8月, 2013 1 次提交
  57. 21 6月, 2013 1 次提交
    • H
      clk: add support for Rockchip gate clocks · 646572c7
      由 Heiko Stübner 提交于 
      This adds basic support for gate-clocks on Rockchip SoCs.
There are 16 gates in each register and use the HIWORD_MASK
mechanism for changing gate settings.

The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all 160 gates can be put into
one gate clock spanning all registers or they can be divided into
the 10 individual gates containing 16 clocks each.
The code supports both approaches.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      646572c7
  59. 20 6月, 2013 1 次提交
  61. 01 6月, 2013 1 次提交
  63. 29 5月, 2013 1 次提交
  65. 27 5月, 2013 1 次提交
  67. 13 4月, 2013 1 次提交
  69. 27 3月, 2013 2 次提交
    • E
      clk: arm: sunxi: Add a new clock driver for sunxi SOCs · e874a669
      由 Emilio López 提交于 
      This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.

Additionally, document the new bindings introduced by this patch.

Idling:
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            60000000
              cpu                   0           0            60000000
                 axi                0           0            60000000
                    ahb             0           0            60000000
                       apb0         0           0            30000000
     dummy                          0           0            0

After "yes >/dev/null &":
    / # cat /sys/kernel/debug/clk/clk_summary
       clock                        enable_cnt  prepare_cnt  rate
    ---------------------------------------------------------------------
     osc32k                         0           0            32768
     osc24M_fixed                   0           0            24000000
        osc24M                      0           0            24000000
           apb1_mux                 0           0            24000000
              apb1                  0           0            24000000
           pll1                     0           0            1008000000
              cpu                   0           0            1008000000
                 axi                0           0            336000000
                    ahb             0           0            168000000
                       apb0         0           0            84000000
     dummy                          0           0            0
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      e874a669
    • P
      clk: Add composite clock type · ece70094
      由 Prashant Gaikwad 提交于 
      Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
      ece70094