Skip to content

K
Kernel

openeuler / Kernel
1 年多 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 21 1月, 2015 7 次提交
    • T
      clk: ppc-corenet: rename driver to clk-qoriq · 93a17c05
      由 Tang Yuantian 提交于 
      Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      93a17c05
    • T
      clock: redefine variable clocks_per_pll as a struct member · 57bfd7ee
      由 Tang Yuantian 提交于 
      redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      57bfd7ee
    • T
      clk: ti: Initialize clocks for dm816x · 1a34275d
      由 Tony Lindgren 提交于 
      The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      1a34275d
    • T
      clk: ti: Add support for FAPLL on dm816x · 163152cb
      由 Tony Lindgren 提交于 
      On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      163152cb
    • S
      clk: Skip fetching index for single parent clocks · 4526e7b8
      由 Stephen Boyd 提交于 
      We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      4526e7b8
    • S
      clk-gate: fix bit # check in clk_register_gate() · 2e9dcdae
      由 Sergei Shtylyov 提交于 
      In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 04577994 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      2e9dcdae
    • K
      clk: ppc-corenet: fix section mismatch warning · 66619ac5
      由 Kevin Hao 提交于 
      In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      66619ac5
  3. 18 1月, 2015 6 次提交
  5. 15 1月, 2015 3 次提交
  7. 14 1月, 2015 2 次提交
  9. 29 12月, 2014 2 次提交
    • H
      clk: rockchip: fix rk3288 cpuclk core dividers · 9880d427
      由 Heiko Stuebner 提交于 
      Commit 0e5bdb3f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.
Reported-by: NSonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
      9880d427
    • H
      clk: rockchip: fix rk3066 pll lock bit location · 12551f02
      由 Heiko Stuebner 提交于 
      The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: NFUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org
      12551f02
  11. 23 12月, 2014 2 次提交
  13. 21 12月, 2014 2 次提交
  15. 20 12月, 2014 4 次提交
  17. 19 12月, 2014 8 次提交
  19. 18 12月, 2014 4 次提交