This patch renames the SPINOR_OP_* macros of the 4-byte address
instruction set so the new names all share a common pattern: the 4-byte
address name is built from the 3-byte address name appending the "_4B"
suffix.

The patch also introduces new op codes to support other SPI protocols such
as SPI 1-4-4 and SPI 1-2-2.

This is a transitional patch and will help a later patch of spi-nor.c
to automate the translation from the 3-byte address op codes into their
4-byte address version.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMark Brown <broonie@kernel.org>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

This driver adds mtd support for the Aspeed AST2400 SoC static memory
controllers:

 * New Static Memory Controller (referred as FMC)
   . BMC firmware
   . AST2500 compatible register set
   . 5 chip select pins (CE0 ∼ CE4)
   . supports NOR flash, NAND flash and SPI flash memory.

 * SPI Flash Controller (SPI)
   . host Firmware
   . slightly different register set, between AST2500 and the legacy
     controller
   . supports SPI flash memory
   . 1 chip select pin (CE0)

The legacy static memory controller (referred as SMC) is not
supported, as well as types other than SPI.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This driver adds mtd support for the Aspeed AST2500 SoC static memory
controllers :

 * Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . supports SPI type flash memory (CE0-CE1)
   . CE2 can be of NOR type flash but this is not supported by the
     driver

 * SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . supports SPI type flash memory

Each controller has a memory range on which it maps its flash module
slaves. Each slave is assigned a memory window for its mapping that
can be changed at bootime with the Segment Address Register.

Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO.

Currently, only the User mode is supported. Command mode needs a
little more work to check that the memory window on the AHB bus fits
the module size.

Based on previous work from Milton D. Miller II <miltonm@us.ibm.com>
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This patch removes the WARN_ONCE() test in spi_nor_write().
This macro triggers the display of a warning message almost every time we
use a UBI file-system because a write operation is performed at offset 64,
which is in the middle of the SPI NOR memory page. This is a valid
operation for ubifs.

Hence this warning is pretty annoying and useless so we just remove it.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Suggested-by: NRichard Weinberger <richard@nod.at>
Suggested-by: NAndras Szemzo <szemzo.andras@gmail.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The patch checks whether the Quad Enable bit is already set in the Status
Register. If so, the function exits immediately with a successful return
code.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>

Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep
their configuration data and (optionally) some user data.

The protocol of this flash follows most of the spi-nor standard. With
the following differences:

- Page size might not be a power of two.
- The address calculation (default addressing mode).
- The spi nor commands used.

Protocol is described on Xilinx User Guide UG333
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The x86-64 and some other architectures are missing readsl/writesl
functions, so this driver won't build on them. Use a more portable
ioread32_rep()/iowrite32_rep() instead.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Graham Moore <grmoore@opensource.altera.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
Suggested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

All fsl_qspi_devtype_data structures are never modified.
This patch constify them.
Signed-off-by: NLABBE Corentin <clabbe.montjoie@gmail.com>
Acked-by: NHan Xu <han.xu@nxp.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add Everspin mr25h40 512KB MRAM to the list of supported chips.
Signed-off-by: NMasahiko Iwamoto <iwamoto@allied-telesis.co.jp>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.

Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids.

Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>
Acked-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

We return success or possibly uninitialized values on these error paths
instead of proper error codes.

Fixes: 14062341 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

There are CQSPI_MAX_CHIPSELECT elements in the ->f_pdata array so the >
should be >=.

Fixes: 14062341 ('mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Signed-off-by: NSean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

The Spansion S25FL128S also supports dual read mode.
In addition remove flag SECT_4K. 4K erases are supported,
but not uniformly.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

With the S25FL127S nor flash part, each writing to the configuration
register takes hundreds of ms. During that  time, no more accesses to
the flash should be done (even reads).

This commit adds a wait loop after the register writing until the flash
finishes its work.

This issue could make rootfs mounting fail when the latter was done too
much closely to this quad enable bit setting step. And in this case, a
driver as UBIFS may try to recover the filesystem and may broke it
completely.
Signed-off-by: NJoël Esponde <joel.esponde@honeywell.com>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

Signed-off-by: NAsh Benz <ash.benz@bk.ru>
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>

This controller driver is used only on ARM but is mostly written
portably so it can build on other arch'es. Unfortunately, at least x86
doesn't provibe readsl()/writesl() accessors. We could possibly fix this
issue in the future by using io{read,write}32_rep() instead, but let's
just drop the architectures we aren't using for now.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Remove duplicated include.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add support for the Cadence QSPI controller. This controller is
present in the Altera SoCFPGA SoCs and this driver has been tested
on the Cyclone V SoC.
Signed-off-by: NGraham Moore <grmoore@opensource.altera.com>
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Graham Moore <grmoore@opensource.altera.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This driver add support to the new Atmel QSPI controller embedded into
sama5d2x SoCs. It expects a NOR memory to be connected to the QSPI
controller.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add hisilicon spi-nor flash controller driver
Signed-off-by: NBinquan Peng <pengbinquan@hisilicon.com>
Signed-off-by: NJiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Gigadevice flash support BP{0,1,2,3,4} bits, where BP3 means the same as
the existing supported TB (Top/Bottom), and BP4 means the same as the
not-yet-supported 4K bit used on other flash (e.g., Winbond). Let's
support lock/unlock with the same feature flags as w25q32dw/w25q64dw.

Tested on gd25lq64c, but I checked datasheets for the other 3, to make
sure.

While I was at it, I noticed that these all support dual and quad as
well. I noted them, but can't test them at the moment, since my test
system only supports standard 1x SPI.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add Micron (n25q00a) 1Gbit NOR Flash in the list of supported
devices.
This part is different from n25q00 in Memory Type.
Memory Type for n25q00 - BAh
Memory Type for n25q00a - BBh
Signed-off-by: NP L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

In stm_unlock(), the test to determine whether we've fully unlocked the
flash checks for the lock length to be equal to the flash size. That is
a typo/think-o -- the condition actually means the flash is completely
*locked.* We should be using the inverse condition -- that the lock
length is 0 (i.e., no protection).

The result of this bug is that we never actually turn off the Status
Register Write Disable bit, even if the flash is completely unlocked.
Now we can.

Fixes: 47b8edbf ("mtd: spi-nor: disallow further writes to SR if WP# is low")
Reported-by: NGiorgio <giorgio.nicole@arcor.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

mtdblock and ubi do not handle the situation when read returns less data
than requested. Loop in spi-nor until buffer is filled or an error is
returned.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMichal Suchanek <hramrach@gmail.com>
Tested-by: NMichal Suchanek <hramrach@gmail.com>

The spi-nor write loop assumes that what is passed to the hardware
driver write() is what gets written.

When write() writes less than page size at once data is dropped on the
floor. Check the amount of data writen and exit if it does not match
requested amount.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMichal Suchanek <hramrach@gmail.com>
Tested-by: NMichal Suchanek <hramrach@gmail.com>

Do not pass retlen to hardware driver read/write functions. Update it in
spi-nor generic driver instead.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMichal Suchanek <hramrach@gmail.com>
Tested-by: NMichal Suchanek <hramrach@gmail.com>

SPI NOR hardware drivers now return useful value from their write
functions so check them.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMichal Suchanek <hramrach@gmail.com>
Tested-by: NMichal Suchanek <hramrach@gmail.com>

Add checking of SPI transfer errors and return them from read/write
functions. Also return the amount of data transferred.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Add checking of SPI transfer errors and return them from read/write
functions. Also return the amount of data transferred.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Return amount of data read/written or error as read(2)/write(2) does.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Change the return value of spi-nor device read and write methods to
allow returning amount of data transferred and errors as
read(2)/write(2) does.

Also, start handling positive returns in spi_nor_read(), since we want
to convert drivers to start returning the read-length both via *retlen
and the return code. (We don't need to do the same transition process
for spi_nor_write(), since ->write() didn't used to have a return code
at all.)
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NMichal Suchanek <hramrach@gmail.com>
Tested-by: NMichal Suchanek <hramrach@gmail.com>

Also note the GigaDevice JEDEC ID.

No write-protect support yet, since this flash uses a different status
register layout.

Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

These are recent Winbond models that are known to have lock/unlock
support via writing the Status Register, and that also support the TB
(Top/Bottom) protection bit.

Tested on w25q32dw.

[Note on style: these entries are getting pretty long lines, so I picked
a style that seems reasonable for splitting up the flags separate from
the other mostly-similar fields.]
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

Some flash support a bit in the status register that inverts protection
so that it applies to the bottom of the flash, not the top. This yields
additions to the protection range table, as noted in the comments.

Because this feature is not universal to all flash that support
lock/unlock, control it via a new flag.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

We can't determine this purely by manufacturer type (see commit
67b9bcd3 ("mtd: spi-nor: fix Spansion regressions (aliased with
Winbond)")), and it's not autodetectable by anything like SFDP. So make
a new flag for it.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

It's a little easier to read and make sure there are no collisions
(IMO).
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

Locking the flash is most useful if it provides real hardware security.
Otherwise, it's little more than a software permission bit.

A reasonable use case that provides real HW security might be like
follows:

(1) hardware WP# is deasserted
(2) program flash
(3) flash range is protected via status register
(4) hardware WP# is asserted
(5) flash protection range can no longer be changed, until WP# is
    deasserted

In this way, flash protection is co-owned by hardware and software.

Now, one would expect to be able to perform step (3) with
ioctl(MEMLOCK), except that the spi-nor driver does not set the Status
Register Protect bit (a.k.a. Status Register Write Disable (SRWD)), so
even though the range is now locked, it does not satisfy step (5) -- it
can still be changed by a call to ioctl(MEMUNLOCK).

So, let's enable status register protection after the first lock
command, and disable protection only when the flash is fully unlocked.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>

There are a few different corner cases to the current logic that seem
undesirable:

* mtd_lock() with offs==0 trips a bounds issue on
  ofs - mtd->erasesize < 0

* mtd_unlock() on the middle of a flash that is already unlocked will
  return -EINVAL

* probably other corner cases

So, let's stop doing "smart" checks like "check the block below us",
let's just do the following:

(a) pass only non-negative offsets/lengths to stm_is_locked_sr()
(b) add a similar stm_is_unlocked_sr() function, so we can check if the
    *entire* range is unlocked (and not just whether some part of it is
    unlocked)

Then armed with (b), we can make lock() and unlock() much more
symmetric:

(c) short-circuit the procedure if there is no work to be done, and
(d) check the entire range above/below

This also aligns well with the structure needed for proper TB
(Top/Bottom) support.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>