On some Intel BXT platform, wake-up from suspend-to-idle on pressing
power-button is not working. Its noticed that gpio-keys driver marking the
second level IRQ/power-button as wake capable but Intel pintctrl
driver is missing to mark GPIO chip/controller IRQ which first level IRQ
as wake cable if its GPIO pin IRQ is wakeble. So, though the first level
IRQ gets generated on power-button press, since it is not marked as
wake capable resume/wake-up flow is not happening.
Intel pintctrl/GPIO driver need to mark GPIO chip/controller IRQ (first
level IRQ) as wake capable iff GPIO pin's IRQ (second level IRQ) is marked
as wake cable.

Changes in v2:
 - Add missing irq initialisation.
Signed-off-by: NNilesh Bacchewar <nilesh.bacchewar@intel.com>
Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This simplifies the error handling and allows us to drop the whole
chv_pinctrl_remove() function.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

It turns out that for north and southwest communities, they can only
generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
part (8-15) can only generate GPEs (General Purpose Events).

Now the reason why EC events such as pressing hotkeys does not work if we
mask all the interrupts is that in order to generate either interrupts or
GPEs the INTMASK register must have that particular interrupt unmasked. In
case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
driver does not see it) but instead it causes SCI (System Control
Interrupt) to be triggered with the GPE in question set.

To make this all work as expected we only add those GPIOs to the IRQ domain
that can actually generate interrupts (IntSel value 0-7) and skip others.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Linux 4.8-rc6

When using GPIO irqchip helpers to setup irqchip for a gpiolib based
driver, it is not possible to select which GPIOs to add to the IRQ domain.
Instead it just adds all GPIOs which is not always desired. For example
there might be GPIOs that for some reason cannot generated normal
interrupts at all.

To support this we add a flag irq_need_valid_mask to struct gpio_chip. When
this flag is set the core allocates irq_valid_mask that holds one bit for
each GPIO the chip has. By default all bits are set but drivers can
manipulate this using set_bit() and clear_bit() accordingly.

Then when gpiochip_irqchip_add() is called, this mask is checked and all
GPIOs with bit is set are added to the IRQ domain created for the GPIO
chip.
Suggested-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is no point in adding any default trigger for these
GPIO interrupts: the device tree should contain all trigger
information and the platforms using the driver boots
exclusively from device tree.

Also the boot log is nagging me to fix this:

[    0.771057] ------------[ cut here ]------------
[    0.775695] WARNING: CPU: 0 PID: 1 at
   ../drivers/gpio/gpiolib.c:1622 _gpiochip_irqchip_add+0x138/0x160
[    0.785034] /soc/gpio@8012e000: Ignoring 2 default trigger
(...)
[    0.942962] gpio 8012e000.gpio: at address e08f8000
(etc ad nauseam)
Suggested-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl dt doc and removes
references to these obsolete platforms. It also updates
the dt example to the currently supported STiH407
platform.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <robh+dt@kernel.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

STiH415/6 SoC support is being removed from the kernel.
This patch updates the ST pinctrl driver and removes
references to these obsolete platforms. As some structures
referenced by STiH407 based configuration were shared with
STiH416 we update these names to match the remaining
supported platform.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Cc: <linus.walleij@linaro.org>
Cc: <linux-gpio@vger.kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add EE domains pins for the i2c devices A,B,C
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The newly added irqchip support for the stm32 pinctrl driver uses
hierarchical IRQ domains as provided by the NVIC primary irqchip.
This works great for any configuration that may be relevant on
stm32, but when doing compile-testing (randconfig), we can
enable it without NVIC or any other primary irqchip that
enables IRQ_DOMAIN_HIERARCHY:

drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function)
drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function)

This adds a Kconfig dependency to limit compile-testing to
configurations that have IRQ_DOMAIN_HIERARCHY already enabled.
It's not obvious whether we should use 'depends on' or 'select'
here, I think either one works, with 'depends on' being more
intuitive, while 'select' would be less likely to cause dependency
loops.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 0eb9f683 ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add EE domains pins for the SPI flash controller
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.9 (take three)

  - Return pinconf with arguments in packed format,
  - MSIOF and QSPI pin groups on R-Car V2H,
  - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.

All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This follows the style of existing PORT_GP_X macros and
will be used by a follow-up patch for the r8a7791 SoC.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

"st,syscfg" entry was bad described.
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

strict pin controller returns -EINVAL in case of pin request which
is already claimed by somebody else.
Following is the sequence of calling pin_request() from
pinctrl_bind_pins():-
pinctrl_bind_pins()->pinctrl_select_state()->pinmux_enable_setting()->
pin_request()

But pinctrl_bind_pins() only returns -EPROBE_DEFER which makes device
driver probe successful even if the pin request is rejected by the pin
controller subsystem.

This commit modifies pinctrl_bind_pins() to return error if the pin is
rejected by pin control subsystem.
Signed-off-by: NDeepak Das <deepak_das@mentor.com>
[Rewrote to be cleaner]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds the SDIO interrupt pin which can be used by sd_emmc_a.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Suggested-by: NNeil Armstrong <narmstrong@baylibre.com>

Fixes: 29885a65 ("pinctrl: meson-gxbb: add the pins for the
SDIO/sd_emmc_a controller")
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The newly added aspeed driver tries to check for a negative return
value from a pinctrl function, but stores the intermediate value in
a 'bool' variable, which cannot work:

drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set':
drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare]

This slightly reworks the logic to use an explicit comparison with zero
before assigning to the temporary variable.
Reported-by: NColin King <colin.king@canonical.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These structures are only used to copy into other structures, so declare
them as const.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };

@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;

@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p

@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
 struct gpio_chip i = { ... };
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These structures are only used to copy into other structures, so declare
them as const.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };

@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;

@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p

@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
 struct gpio_chip i = { ... };
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The earlier patch can be simplified by using a bool
to indicate level trigger.
Reviewed-by: NPankaj Sen <Pankaj.Sen@amd.com>
Signed-off-by: NNitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
[Fixup to earlier manually applied patch]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds IRQ support to STM32 gpios.

The EXTI controller has 16 lines dedicated to GPIOs.
EXTI line n can be connected to only line n of one of the GPIO ports, for
example EXTI0 can be connected to either PA0, or PB0, or PC0...
This port selection is done by specifying the port number into System
Config registers.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

samsung_pinctrl_probe() can be called only after matching
the driver by the compatible string so this already implies
a non null dev->of_node.  Remove the always false test
and related error trace. While at it drop another error log
in case of memory allocation failure - any errors are logged
by the memory subsystem.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In function mrfld_pinctrl_probe(), when duplicating the mrfld_families
array the requested memory region length is multiplied once too many by the
number of elements in the original array. Fix this to spare some memory.

Fixes: 4e80c8f5 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: NVincent Stehlé <vincent.stehle@intel.com>
Acked-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If a GPIO controller description in board DTB contains information
about mappings between GPIOs and pads under IOMUX control use it to
request and free GPIOs with respect to pinctrl/pinmux subsystems.

One of immediate positive functional changes is inability to
request non-existing GPIOs, i.e. if there is no pad such. Also
pinctrl/pinmux may now properly account pads occupied by requested
GPIOs.

The change has no effect, if "gpio-ranges" property is not found
including the case if a board has no DTB firmware.
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In general situation on-SoC GPIO controller drivers should be probed
after pinctrl/pinmux controller driver, because on-SoC GPIOs utilize a
pin/pad as a resource provided and controlled by pinctrl subsystem.

This is stated in multiple places, e.g. from drivers/Makefile:

  GPIO must come after pinctrl as gpios may need to mux pins etc

Looking at Freescale iMX SoC series specifics, imx*_pinctrl_init()
functions are called at arch_initcall and postcore_initcall init
levels, so the change of initcall level for gpio-mxc driver from
postcore_initcall to subsys_initcall level is sufficient. Also note
that the most of GPIO controller drivers settled at subsys_initcall
level.

If pinctrl subsystem manages pads with GPIO functions, the change is
needed to avoid unwanted driver probe deferrals during kernel boot.
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

While only Freescale Vybrid SoC has settings of GPIO capabilities done
by iomux controller, it is only a matter of GPIO controller driver
implementation for the rest of Freescale/NXP SoCs from iMX series.

As a practical example on GPIO request a pad function should be
switched to GPIO, but because this requires updates to all particular
iMX pinctrl drivers, for simplicity at the moment add only a proper
connection between shared pinctrl-imx and pinctrl/pinmux core, namely
.gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks
should return success to a caller. This change allows to progress by
adding request/free callbacks into gpio-mxc.c driver.
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

at91 used to set a default trigger type for GPIO interrupts in
order to cope with the old board files. These days are long gone,
and it all gets probed through DT.

Andras Szemzo reported that the Ethernet device on his board was
bailing to be probed, due to a conflict in interrupt trigger.
Surely enough, this is due to this default trigger still being
present, and turning this into a IRQ_TYPE_NONE fixes the issue.
Reported-by: NAndras Szemzo <szemzo.andras@gmail.com>
Tested-by: NAndras Szemzo <szemzo.andras@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch supports the {get,set}_io_voltage operations of SDHI.

This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v
voltage switch.

Based on work by Takeshi Kihara and Wolfram Sang.

Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The pinconf-generic code expects configurations with arguments to be
returned in a packed format in order to be displayed properly by
pinconf_generic_dump_one().

Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on
r8a7795/salvator-x now shows:

    pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector)

Instead of:

    pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector)
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add MSIOF0/1 pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add QSPI pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Commit aa719874 ("nvme: fabrics drivers don't need the nvme-pci
driver") removed the dependency on BLK_DEV_NVME, but the cdoe does
depend on the block layer (which used to be an implicit dependency
through BLK_DEV_NVME).

Otherwise you get various errors from the kbuild test robot random
config testing when that happens to hit a configuration with BLOCK
device support disabled.

Cc: Christoph Hellwig <hch@lst.de>
Cc: Jay Freyensee <james_p_freyensee@linux.intel.com>
Cc: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Pull IIO fixes from Greg KH:
 "Here are a few small IIO fixes for 4.8-rc6.

  Nothing major, full details are in the shortlog, all of these have
  been in linux-next with no reported issues"

* tag 'staging-4.8-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  iio:core: fix IIO_VAL_FRACTIONAL sign handling
  iio: ensure ret is initialized to zero before entering do loop
  iio: accel: kxsd9: Fix scaling bug
  iio: accel: bmc150: reset chip at init time
  iio: fix pressure data output unit in hid-sensor-attributes
  tools:iio:iio_generic_buffer: fix trigger-less mode