Merge "Xilinx Zynq dt changes for v3.17 - third pull request" from Michal
Simek:

arm: Xilinx Zynq dt patches for v3.17 third pull request

- Add Adapteva Parallella board/DT
- Add SPI nodes
- Add CAN nodes
- Clean Zynq description

* tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: DT: Clarify Xilinx Zynq platform
  ARM: zynq: DT: Remove DMA from board DTs
  ARM: zynq: DT: Add CAN node
  ARM: dts: zynq: Add SPI
  ARM: dts: zynq: Add DMAC for Parallella
  ARM: dts: zynq: Add Parallella device tree
  Documentation: devicetree: Adapteva boards
  Documentation: devicetree: Adapteva vendor prefix
Signed-off-by: NOlof Johansson <olof@lixom.net>

Working on sound support I noticed the Apalis T30 Evaluation board
device tree missing the more generic Apalis T30 compatible string.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Indentation of the clock property used a hodgepodge of tabs and spaces.
Make them more consistent (tabs for indentation followed by spaces for
alignment).
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'renesas-clock3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Third Round of Renesas ARM Based SoC Clock Updates for v3.17" from Simon
Horman:

Third Round of Renesas ARM Based SoC Clock Updates for v3.17

* Add legacy clocks for SCI for SoCs that do not yet have CCF support.
  This is to allow timer devices to be enabled using DT and
  will be removed after CCF support is added for each SoC.

  This is in keeping with the approach taken for enabling
  SCI (serial) devices using DT on these SoCs.

* tag 'renesas-clock3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: sh73a0: add CMT1 clock support for DT
  ARM: shmobile: r8a7740: add CMT1 clock support for DT
  ARM: shmobile: r8a73a4: add CMT1 clock support for DT
  ARM: shmobile: r8a7740: add TMU clock support for DT
  ARM: shmobile: r8a7778: add TMU clock support for DT
Signed-off-by: NOlof Johansson <olof@lixom.net>

ep107 was emulation platform and compatible string
have been changed long time ago.

"ARM: zynq: dts: split up device tree"
(sha1: e06f1a9e)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The DMA engine is enabled for all DTs that derive from zynq-7000.dtsi.
There is no need to override the 'status' property in board DTs.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add node describing Zynq's CAN controller.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

Merge "ARM: mach-bcm: dt updatees for 3.17" from Matt Porter:

- BCM Mobile SMP support
- BRCM STB platform support

* tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm:
  ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
  ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
  ARM: brcmstb: add misc. DT bindings for brcmstb
  ARM: brcmstb: add CPU binding for Broadcom Brahma15
  ARM: dts: enable SMP support for bcm21664
  ARM: dts: enable SMP support for bcm28155
  devicetree: bindings: document Broadcom CPU enable method
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Update to Linux 3.16-rc6 as a dependency for the broadcom changes.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Merge "mvebu DT changes for v3.17 (round 4)" from Jason Cooper"

 - Armada XP
    - New board, Lenovo ix4-300d NAS
    - Add Lenovo to vendor-prefixes

 - Dove
    - Add LCD controllers

* tag 'mvebu-dt-3.17-4' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Add dts definition for Lenovo Iomega ix4-300d NAS
  of: Add Lenovo Group Ltd. to the vendor-prefixes list.
  ARM: dts: dove: add DT LCD controllers
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add a sample DTS which will allow bootup of a board populated
with the BCM7445 chip.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Cc: Matt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Document the Broadcom Brahma B15 GIC implementation as compatible
with the ARM GIC standard.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Document the bindings that the Broadcom STB platform needs
for proper bootup.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NMatt Porter <mporter@linaro.org>

The Lenovo Iomega ix4-300d is a 4-Bay sata NAS with dual Gb, USB2.0 & 3.0,
powered by a Marvell Armada XP MV78230 dual core CPU.

http://shop.lenovo.com/us/en/servers/network-storage/lenovoemc/ix4-300d/Signed-off-by: NBenoit Masson <yahoo@perenite.com>
Link: https://lkml.kernel.org/r/1406503839-4662-1-git-send-email-yahoo@perenite.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Define nodes representing the two Cortex A9 CPUs in a bcm21644 SoC.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Define nodes representing the two Cortex A9 CPUs in a bcm28155 SoC.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Broadcom mobile SoCs use a ROM-implemented holding pen for
controlled boot of secondary cores.  A special register is
used to communicate to the ROM that a secondary core should
start executing kernel code.  This enable method is currently
used for members of the bcm281xx and bcm21664 SoC families.

The use of an enable method also allows the SMP operation vector to
be assigned as a result of device tree content for these SoCs.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Lenovo Group Ltd. (stylized as lenovo) is a Chinese multinational computer
technology company with headquarters in Beijing, China, and Morrisville, North
Carolina, United States.

http://www.lenovo.com/Signed-off-by: NBenoit Masson <yahoo@perenite.com>
Acked-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1406154923-13612-1-git-send-email-yahoo@perenite.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Merge tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "ARM: dts: changes for existing rockchip boards" from Heiko Stuebner:

Collected changes for existing Rockchip boards
- convert to new clock driver
- bring structure in line with recent rk3288 comments
  (no soc-nodes, using phandles when adding changes, sorted by address)
- i2c, board-pmic and pwm nodes nodes
- sd card slot and ir receiver on radxa rock

* tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rk3188-radxarock: add GPIO IR receiver node
  ARM: dts: rockchip: add pwm nodes
  ARM: dts: rockchip: add both clocks to uart nodes
  ARM: dts: rk3188-radxarock: enable sd-card slot
  ARM: dts: add i2c and regulator nodes to rk3188-radxarock
  ARM: dts: rockchip: add tps65910 regulator for bqcurie2
  ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings
  ARM: dts: rockchip: oder nodes by register address
  ARM: dts: rockchip: remove address from pinctrl nodes
  ARM: dts: uses handles to reference nodes for changes
  ARM: dts: rockchip: add handles for shared nodes that don't have one yet
  ARM: dts: rockchip: remove soc subnodes
  arm: dts: rockchip: remove obsolete clock gate definitions
  ARM: dts: rockchip: move oscillator input clock into main dtsi
  ARM: dts: rockchip: add cru nodes and update device clocks to use it
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Merge tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "Initial support for Rockchip RK3288 SoCs" from Heiko Stuebner:

* tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: Build dtbs for Rockchip boards
  ARM: dts: add rk3288 evaluation board
  ARM: dts: rockchip: add core rk3288 dtsi
  ARM: rockchip: enable support for RK3288 SoCs
  ARM: Kconfig: set default gpio number for rockchip SoCs
  ARM: rockchip: add debug uart used by rk3288
  ARM: rockchip: clarify usability of DEBUG_RK3X_UART debug_ll options
  dt-bindings: arm: add cortex-a12 and cortex-a17 cpu compatible properties
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This is a dependency for the rk3288 DT updates, the branch should
first get merged through Mike's clk git.

* 'clk-rockchip' of git://git.linaro.org/people/mike.turquette/linux:
  ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER
  clk: rockchip: add clock controller for rk3288
  dt-bindings: add documentation for rk3288 cru
  clk: rockchip: add clock driver for rk3188 and rk3066 clocks
  dt-bindings: add documentation for rk3188 clock and reset unit
  clk: rockchip: add reset controller
  clk: rockchip: add clock type for pll clocks and pll used on rk3066
  clk: rockchip: add basic infrastructure for clock branches
  clk: composite: improve rate_hw sanity check logic
  clk: composite: allow read-only clocks
  clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This adds a device tree node for the infrared receiver connected to a
GPIO pin on the Radxa Rock.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>

Modified to use the new clock defines and added rk3066 pins.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use the newly ammended dw_8250 clock binding to define both the baudclk as
well as the pclk supplying the ip.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Radxa Rock contains one sd-card slot. Add the supplying regulator
and enable its dw_mmc node.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This enables the 2nd i2c bus and adds the act8846 pmic as device.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Curie2 uses a tps659102 as its main pmic, so add the i2c1 and tps65910
node as well as define the used voltages and regulator-names according to
the schematics.

Also fix the supply of the sd0 regulator, as it is supplied by the vio reg.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The core controller settings themself are identical, only the compatible and
pinctrl settings differ.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

To create some sort of ordering of nodes, they are suggested to be ordered by
their register address.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The pincontroller uses the GRF and PMU syscons nowadays, so should not
contain an address in its device node.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use the handles for subsequent changes to nodes, similar to like the rk3288
submission does it.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Some nodes that are changed in the dtsi hierarchy do not have handles yet.
As it was suggested in the rk3288 submission to do subsequent nodes changes
through such handle-references, add the missing ones.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Comments received from the rk3288 submission indicated that a generic subnode
to group soc components should not be used.

So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The clock and reset unit is now provided by the rk3188-cru clock driver and thus
the old style definitions of the gate clocks can go away.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

The clock definitions get a lot shorter due to the soc clocks being handled by
rk3188-cru and only the input clock remains. These can now simply live
in the main rk3xxx.dtsi without affecting readability.

At the same time, rename the node to oscillator, adding a clock-output-names
property to match how the rk3288 handles this.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and
also updates the device nodes retrieve their clocks from there, instead of
the previous gate clock nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

This allows the "make dtbs" target to work.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>

There exist 2 variants using either the act8846 or rk808 as pmic, while the
rest of the board stays the same.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>