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  1. 20 8月, 2009 1 次提交
  3. 30 7月, 2009 1 次提交
    • A
      powerpc/83xx: Fix PCI IO base address on MPC837xE-RDB boards · 1333c3d6
      由 Anton Vorontsov 提交于 
      U-Boot maps PCI IO at 0xe0300000, while current dts files specify
0xe2000000. This leads to the following oops with CONFIG_8139TOO_PIO=y.

8139too Fast Ethernet driver 0.9.28
Machine check in kernel mode.
Caused by (from SRR1=41000): Transfer error ack signal
Oops: Machine check, sig: 7 [#1]
MPC837x RDB
[...]
NIP [00000900] 0x900
LR [c0439df8] rtl8139_init_board+0x238/0x524
Call Trace:
[cf831d90] [c0439dcc] rtl8139_init_board+0x20c/0x524 (unreliable)
[cf831de0] [c043a15c] rtl8139_init_one+0x78/0x65c
[cf831e40] [c0235250] pci_call_probe+0x20/0x30
[...]

This patch fixes the issue by specifying the correct PCI IO base
address.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      1333c3d6
  5. 16 6月, 2009 1 次提交
  7. 24 3月, 2009 2 次提交
    • A
      powerpc/83xx: Move gianfar mdio nodes under the ethernet nodes · 70b3adbb
      由 Anton Vorontsov 提交于 
      Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      70b3adbb
    • A
      powerpc/83xx: Add power management support for MPC837x boards · 125a00d7
      由 Anton Vorontsov 提交于 
      This patch adds pmc nodes to the device tree files so that the boards
will able to use standby capability of MPC837x processors. The MPC837x
PMC controllers are compatible with MPC8349 ones (i.e. no deep sleep).

sleep = <> properties are used to specify SCCR masks as described
in "Specifying Device Power Management Information (sleep property)"
chapter in Documentation/powerpc/booting-without-of.txt.

Since I2C1 and eSDHC controllers share the same clock source, they
are now placed under sleep-nexus nodes.

A processor is able to wakeup the boards on LAN events (Wake-On-Lan),
console events (with no_console_suspend kernel command line), GPIO
events and external IRQs (IRQ1 and IRQ2).

The processor can also wakeup the boards by the fourth general purpose
timer in GTM1 block, but the GTM wakeup support isn't yet implemented
(it's tested to work, but it's unclear how can we use the quite short
GTM timers, and how do we want to expose the GTM to userspace).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      125a00d7
  9. 07 2月, 2009 1 次提交
  11. 03 2月, 2009 1 次提交
  13. 02 2月, 2009 1 次提交
  15. 29 1月, 2009 2 次提交
  17. 17 12月, 2008 1 次提交
  19. 05 11月, 2008 1 次提交
  21. 21 10月, 2008 1 次提交
  23. 14 10月, 2008 1 次提交
    • J
      powerpc: 83xx: pci: Remove need for get_immrbase from mpc83xx_add_bridge. · 5b70a097
      由 John Rigby 提交于 
      Modify mpc83xx_add_bridge to get config space register base address from
the device tree instead of immr + hardcoded offset.

83xx pci nodes have this change:
    register properties now contain two address length tuples:
	First is the pci bridge register base, this has always been there.
	Second is the config base, this is new.

This is documented in dts-bindings/fsl/83xx-512x-pci.txt

The changes accomplish these things:
    mpc83xx_add_bridge no longer needs to call get_immrbase
    it uses hard coded addresses if the second register value is missing
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      5b70a097
  25. 24 9月, 2008 1 次提交
  27. 14 7月, 2008 1 次提交
  29. 28 6月, 2008 1 次提交
  31. 10 6月, 2008 1 次提交
  33. 31 3月, 2008 1 次提交
  35. 29 1月, 2008 2 次提交
  37. 28 1月, 2008 3 次提交
  39. 24 1月, 2008 3 次提交
  41. 12 12月, 2007 3 次提交
  43. 08 10月, 2007 1 次提交
  45. 14 9月, 2007 2 次提交
    • K
      [POWERPC] Move PCI nodes to be sibilings with SOC nodes · 1b3c5cda
      由 Kumar Gala 提交于 
      Updated the device trees to have the PCI nodes be at the same level as
the SOC node.  This is to make it so that the SOC nodes children address
space is just on chip registers and not other bus memory as well.

Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge
that exists in the PHB.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      1b3c5cda
    • K
      [POWERPC] DTS cleanup · f0c8ac80
      由 Kumar Gala 提交于 
      Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
* Removed big-endian from i8259 pic nodes, this was just bogus
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      f0c8ac80
  47. 23 7月, 2007 1 次提交
  49. 09 3月, 2007 1 次提交
  51. 17 2月, 2007 1 次提交
  53. 08 2月, 2007 1 次提交
  55. 06 10月, 2006 1 次提交
  57. 14 9月, 2006 1 次提交
  59. 30 8月, 2006 1 次提交