1. 02 7月, 2021 2 次提交
    • G
      octeontx2-af: cn10k: Support configurable LMTST regions · 893ae972
      Geetha sowjanya 提交于
      This patch extends the lmtst_tbl_setup_req mbox to support run time
      LMTST configuration.
      RVU PF/VF and DPDK/ODP allocates a LMT region, creates a translation
      entry for a device via VFIO IOCTLs.
      This IOVA is shared with AF through above mbox. AF then uses
      RVU_SMMU transulation Widget and gets PA for the IOVA and updates
      the LMTtable entry for that device.
      Signed-off-by: NGeetha sowjanya <gakula@marvell.com>
      Signed-off-by: NSunil Kovvuri Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      893ae972
    • H
      octeontx2-af: cn10k: Setting up lmtst map table · 873a1e3d
      Harman Kalra 提交于
      Introducing a new mailbox to support updating lmt entries
      and common lmt base address scheme i.e. multiple pcifuncs
      can share lmt region to reduce L1 cache pressure for application.
      Parameters passed to mailbox includes the primary pcifunc
      value whose lmt regions will be shared by other secondary
      pcifuncs. Here secondary pcifunc will be the one who is
      calling the mailbox.
      For example:
      By default each pcifunc has its own LMT base address:
              PCIFUNC1    LMT_BASE_ADDR A
              PCIFUNC2    LMT_BASE_ADDR B
              PCIFUNC3    LMT_BASE_ADDR C
              PCIFUNC4    LMT_BASE_ADDR D
      Application will choose PCIFUNC1 as base/primary pcifunc
      and as and when other pcifunc(secondary pcifuncs) gets
      probed, this mailbox will be called and LMTST table will
      be updated as:
              PCIFUNC1    LMT_BASE_ADDR A
              PCIFUNC2    LMT_BASE_ADDR A
              PCIFUNC3    LMT_BASE_ADDR A
              PCIFUNC4    LMT_BASE_ADDR A
      
      On FLR lmtst map table gets resetted to the default lmt
      base addresses for all secondary pcifuncs.
      Signed-off-by: NHarman Kalra <hkalra@marvell.com>
      Signed-off-by: NGeetha sowjanya <gakula@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      873a1e3d
  2. 30 6月, 2021 5 次提交
  3. 29 6月, 2021 17 次提交
  4. 26 6月, 2021 14 次提交
    • R
      net/mlx5e: Add IPsec support to uplink representor · 5589b8f1
      Raed Salem 提交于
      Add the xfrm xdo and ipsec_init/cleanup to uplink representor to
      support IPsec in SRIOV switchdev mode.
      Signed-off-by: NRaed Salem <raeds@nvidia.com>
      Signed-off-by: NHuy Nguyen <huyn@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      5589b8f1
    • T
      net/mlx5e: kTLS, Add stats for number of deleted kTLS TX offloaded connections · e8c82761
      Tariq Toukan 提交于
      Expose ethtool SW counter for the number of kTLS device-offloaded
      TX connections that are finished and deleted.
      Signed-off-by: NTariq Toukan <tariqt@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      e8c82761
    • E
      net/mlx5: SF, Improve performance in SF allocation · 5bd8cee2
      Eli Cohen 提交于
      Avoid second traversal on the SF table by recording the first free entry
      and using it in case the looked up entry was not found in the table.
      Signed-off-by: NEli Cohen <elic@nvidia.com>
      Signed-off-by: NParav Pandit <parav@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      5bd8cee2
    • A
      net/mlx5: Increase hairpin buffer size · 6cdc686a
      Ariel Levkovich 提交于
      The max packet size a hairpin queue is able to handle
      is determined by the total hairpin buffer size divided
      by 4.
      
      Currently the buffer size is set to 32KB which makes
      the max packet size to be 8KB and doesn't support
      jumbo frames of size 9KB.
      
      This change increases the buffer size to 64KB to increase
      the max frame size and support 9KB frames.
      Signed-off-by: NAriel Levkovich <lariel@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      6cdc686a
    • Y
      net/mlx5: DR, Add support for flow sampler offload · 1ab6dc35
      Yevgeny Kliteynik 提交于
      Add SW steering support for sFlow / flow sampler action.
      Signed-off-by: NYevgeny Kliteynik <kliteyn@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      1ab6dc35
    • Y
      net/mlx5: Compare sampler flow destination ID in fs_core · 6f851556
      Yevgeny Kliteynik 提交于
      When comparing sampler flow destinations,
      in fs_core, consider sampler ID as well.
      Signed-off-by: NYevgeny Kliteynik <kliteyn@nvidia.com>
      Signed-off-by: NSaeed Mahameed <saeedm@nvidia.com>
      6f851556
    • M
      net: mdiobus: withdraw fwnode_mdbiobus_register · ac53c264
      Marcin Wojtas 提交于
      The newly implemented fwnode_mdbiobus_register turned out to be
      problematic - in case the fwnode_/of_/acpi_mdio are built as
      modules, a dependency cycle can be observed during the depmod phase of
      modules_install, eg.:
      
      depmod: ERROR: Cycle detected: fwnode_mdio -> of_mdio -> fwnode_mdio
      depmod: ERROR: Found 2 modules in dependency cycles!
      
      OR:
      
      depmod: ERROR: Cycle detected: acpi_mdio -> fwnode_mdio -> acpi_mdio
      depmod: ERROR: Found 2 modules in dependency cycles!
      
      A possible solution could be to rework fwnode_mdiobus_register,
      so that to merge the contents of acpi_mdiobus_register and
      of_mdiobus_register. However feasible, such change would
      be very intrusive and affect huge amount of the of_mdiobus_register
      users.
      
      Since there are currently 2 users of ACPI and MDIO
      (xgmac_mdio and mvmdio), withdraw the fwnode_mdbiobus_register
      and roll back to a simple 'if' condition in affected drivers.
      
      Fixes: 62a6ef6a ("net: mdiobus: Introduce fwnode_mdbiobus_register()")
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ac53c264
    • P
      Revert "be2net: disable bh with spin_lock in be_process_mcc" · d6765985
      Petr Oros 提交于
      Patch was based on wrong presumption that be_poll can be called only
      from bh context. It reintroducing old regression (also reverted) and
      causing deadlock when we use netconsole with benet in bonding.
      
      Old revert: commit 072a9c48 ("netpoll: revert 6bdb7fe3 and fix
      be_poll() instead")
      
      [  331.269715] bond0: (slave enp0s7f0): Releasing backup interface
      [  331.270121] CPU: 4 PID: 1479 Comm: ifenslave Not tainted 5.13.0-rc7+ #2
      [  331.270122] Call Trace:
      [  331.270122] [c00000001789f200] [c0000000008c505c] dump_stack+0x100/0x174 (unreliable)
      [  331.270124] [c00000001789f240] [c008000001238b9c] be_poll+0x64/0xe90 [be2net]
      [  331.270125] [c00000001789f330] [c000000000d1e6e4] netpoll_poll_dev+0x174/0x3d0
      [  331.270127] [c00000001789f400] [c008000001bc167c] bond_poll_controller+0xb4/0x130 [bonding]
      [  331.270128] [c00000001789f450] [c000000000d1e624] netpoll_poll_dev+0xb4/0x3d0
      [  331.270129] [c00000001789f520] [c000000000d1ed88] netpoll_send_skb+0x448/0x470
      [  331.270130] [c00000001789f5d0] [c0080000011f14f8] write_msg+0x180/0x1b0 [netconsole]
      [  331.270131] [c00000001789f640] [c000000000230c0c] console_unlock+0x54c/0x790
      [  331.270132] [c00000001789f7b0] [c000000000233098] vprintk_emit+0x2d8/0x450
      [  331.270133] [c00000001789f810] [c000000000234758] vprintk+0xc8/0x270
      [  331.270134] [c00000001789f850] [c000000000233c28] printk+0x40/0x54
      [  331.270135] [c00000001789f870] [c000000000ccf908] __netdev_printk+0x150/0x198
      [  331.270136] [c00000001789f910] [c000000000ccfdb4] netdev_info+0x68/0x94
      [  331.270137] [c00000001789f950] [c008000001bcbd70] __bond_release_one+0x188/0x6b0 [bonding]
      [  331.270138] [c00000001789faa0] [c008000001bcc6f4] bond_do_ioctl+0x42c/0x490 [bonding]
      [  331.270139] [c00000001789fb60] [c000000000d0d17c] dev_ifsioc+0x17c/0x400
      [  331.270140] [c00000001789fbc0] [c000000000d0db70] dev_ioctl+0x390/0x890
      [  331.270141] [c00000001789fc10] [c000000000c7c76c] sock_do_ioctl+0xac/0x1b0
      [  331.270142] [c00000001789fc90] [c000000000c7ffac] sock_ioctl+0x31c/0x6e0
      [  331.270143] [c00000001789fd60] [c0000000005b9728] sys_ioctl+0xf8/0x150
      [  331.270145] [c00000001789fdb0] [c0000000000336c0] system_call_exception+0x160/0x2f0
      [  331.270146] [c00000001789fe10] [c00000000000d35c] system_call_common+0xec/0x278
      [  331.270147] --- interrupt: c00 at 0x7fffa6c6ec00
      [  331.270147] NIP:  00007fffa6c6ec00 LR: 0000000105c4185c CTR: 0000000000000000
      [  331.270148] REGS: c00000001789fe80 TRAP: 0c00   Not tainted  (5.13.0-rc7+)
      [  331.270148] MSR:  800000000280f033 <SF,VEC,VSX,EE,PR,FP,ME,IR,DR,RI,LE>  CR: 28000428  XER: 00000000
      [  331.270155] IRQMASK: 0
      [  331.270156] GPR00: 0000000000000036 00007fffd494d5b0 00007fffa6d57100 0000000000000003
      [  331.270158] GPR04: 0000000000008991 00007fffd494d6d0 0000000000000008 00007fffd494f28c
      [  331.270161] GPR08: 0000000000000003 0000000000000000 0000000000000000 0000000000000000
      [  331.270164] GPR12: 0000000000000000 00007fffa6dfa220 0000000000000000 0000000000000000
      [  331.270167] GPR16: 0000000105c44880 0000000000000000 0000000105c60088 0000000105c60318
      [  331.270170] GPR20: 0000000105c602c0 0000000105c44560 0000000000000000 0000000000000000
      [  331.270172] GPR24: 00007fffd494dc50 00007fffd494d6a8 0000000105c60008 00007fffd494d6d0
      [  331.270175] GPR28: 00007fffd494f27e 0000000105c6026c 00007fffd494f284 0000000000000000
      [  331.270178] NIP [00007fffa6c6ec00] 0x7fffa6c6ec00
      [  331.270178] LR [0000000105c4185c] 0x105c4185c
      [  331.270179] --- interrupt: c00
      
      This reverts commit d0d006a4.
      
      Fixes: d0d006a4 ("be2net: disable bh with spin_lock in be_process_mcc")
      Signed-off-by: NPetr Oros <poros@redhat.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d6765985
    • C
      ice: Fix a memory leak in an error handling path in 'ice_pf_dcb_cfg()' · b81c191c
      Christophe JAILLET 提交于
      If this 'kzalloc()' fails we must free some resources as in all the other
      error handling paths of this function.
      
      Fixes: 348048e7 ("ice: Implement iidc operations")
      Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
      Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
      b81c191c
    • T
      ice: remove unnecessary VSI assignment · 70fa0a07
      Tony Nguyen 提交于
      ice_get_vf_vsi() is being called twice for the same VSI. Remove the
      unnecessary call/assignment.
      Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
      Tested-by: NTony Brelinski <tonyx.brelinski@intel.com>
      70fa0a07
    • V
      ice: remove the VSI info from previous agg · 37c59206
      Victor Raj 提交于
      Remove the VSI info from previous aggregator after moving the VSI to a
      new aggregator.
      Signed-off-by: NVictor Raj <victor.raj@intel.com>
      Tested-by: NTony Brelinski <tonyx.brelinski@intel.com>
      Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
      37c59206
    • M
      ice: add support for auxiliary input/output pins · 172db5f9
      Maciej Machnikowski 提交于
      The E810 device supports programmable pins for enabling both input and
      output events related to the PTP hardware clock. This includes both
      output signals with programmable period, as well as timestamping of
      events on input pins.
      
      Add support for enabling these using the CONFIG_PTP_1588_CLOCK
      interface.
      
      This allows programming the software defined pins to take advantage of
      the hardware clock features.
      Signed-off-by: NMaciej Machnikowski <maciej.machnikowski@intel.com>
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
      172db5f9
    • B
      gve: Fix swapped vars when fetching max queues · 1db1a862
      Bailey Forrest 提交于
      Fixes: 893ce44d ("gve: Add basic driver framework for Compute Engine Virtual NIC")
      Signed-off-by: NBailey Forrest <bcf@google.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1db1a862
    • D
      Add Mellanox BlueField Gigabit Ethernet driver · f92e1869
      David Thompson 提交于
      This patch adds build and driver logic for the "mlxbf_gige"
      Ethernet driver from Mellanox Technologies. The second
      generation BlueField SoC from Mellanox supports an
      out-of-band GigaBit Ethernet management port to the Arm
      subsystem.  This driver supports TCP/IP network connectivity
      for that port, and provides back-end routines to handle
      basic ethtool requests.
      
      The driver interfaces to the Gigabit Ethernet block of
      BlueField SoC via MMIO accesses to registers, which contain
      control information or pointers describing transmit and
      receive resources.  There is a single transmit queue, and
      the port supports transmit ring sizes of 4 to 256 entries.
      There is a single receive queue, and the port supports
      receive ring sizes of 32 to 32K entries. The transmit and
      receive rings are allocated from DMA coherent memory. There
      is a 16-bit producer and consumer index per ring to denote
      software ownership and hardware ownership, respectively.
      
      The main driver logic such as probe(), remove(), and netdev
      ops are in "mlxbf_gige_main.c".  Logic in "mlxbf_gige_rx.c"
      and "mlxbf_gige_tx.c" handles the packet processing for
      receive and transmit respectively.
      
      The logic in "mlxbf_gige_ethtool.c" supports the handling
      of some basic ethtool requests: get driver info, get ring
      parameters, get registers, and get statistics.
      
      The logic in "mlxbf_gige_mdio.c" is the driver controlling
      the Mellanox BlueField hardware that interacts with a PHY
      device via MDIO/MDC pins.  This driver does the following:
        - At driver probe time, it configures several BlueField MDIO
          parameters such as sample rate, full drive, voltage and MDC
        - It defines functions to read and write MDIO registers and
          registers the MDIO bus.
        - It defines the phy interrupt handler reporting a
          link up/down status change
        - This driver's probe is invoked from the main driver logic
          while the phy interrupt handler is registered in ndo_open.
      
      Driver limitations
        - Only supports 1Gbps speed
        - Only supports GMII protocol
        - Supports maximum packet size of 2KB
        - Does not support scatter-gather buffering
      
      Testing
        - Successful build of kernel for ARM64, ARM32, X86_64
        - Tested ARM64 build on FastModels & Palladium
        - Tested ARM64 build on several Mellanox boards that are built with
          the BlueField-2 SoC.  The testing includes coverage in the areas
          of networking (e.g. ping, iperf, ifconfig, route), file transfers
          (e.g. SCP), and various ethtool options relevant to this driver.
      Signed-off-by: NDavid Thompson <davthompson@nvidia.com>
      Signed-off-by: NAsmaa Mnebhi <asmaa@nvidia.com>
      Reviewed-by: NLiming Sun <limings@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f92e1869
  5. 25 6月, 2021 2 次提交