1. 02 7月, 2021 2 次提交
    • G
      octeontx2-af: cn10k: Support configurable LMTST regions · 893ae972
      Geetha sowjanya 提交于
      This patch extends the lmtst_tbl_setup_req mbox to support run time
      LMTST configuration.
      RVU PF/VF and DPDK/ODP allocates a LMT region, creates a translation
      entry for a device via VFIO IOCTLs.
      This IOVA is shared with AF through above mbox. AF then uses
      RVU_SMMU transulation Widget and gets PA for the IOVA and updates
      the LMTtable entry for that device.
      Signed-off-by: NGeetha sowjanya <gakula@marvell.com>
      Signed-off-by: NSunil Kovvuri Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      893ae972
    • H
      octeontx2-af: cn10k: Setting up lmtst map table · 873a1e3d
      Harman Kalra 提交于
      Introducing a new mailbox to support updating lmt entries
      and common lmt base address scheme i.e. multiple pcifuncs
      can share lmt region to reduce L1 cache pressure for application.
      Parameters passed to mailbox includes the primary pcifunc
      value whose lmt regions will be shared by other secondary
      pcifuncs. Here secondary pcifunc will be the one who is
      calling the mailbox.
      For example:
      By default each pcifunc has its own LMT base address:
              PCIFUNC1    LMT_BASE_ADDR A
              PCIFUNC2    LMT_BASE_ADDR B
              PCIFUNC3    LMT_BASE_ADDR C
              PCIFUNC4    LMT_BASE_ADDR D
      Application will choose PCIFUNC1 as base/primary pcifunc
      and as and when other pcifunc(secondary pcifuncs) gets
      probed, this mailbox will be called and LMTST table will
      be updated as:
              PCIFUNC1    LMT_BASE_ADDR A
              PCIFUNC2    LMT_BASE_ADDR A
              PCIFUNC3    LMT_BASE_ADDR A
              PCIFUNC4    LMT_BASE_ADDR A
      
      On FLR lmtst map table gets resetted to the default lmt
      base addresses for all secondary pcifuncs.
      Signed-off-by: NHarman Kalra <hkalra@marvell.com>
      Signed-off-by: NGeetha sowjanya <gakula@marvell.com>
      Signed-off-by: NSunil Goutham <sgoutham@marvell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      873a1e3d
  2. 30 6月, 2021 17 次提交
  3. 29 6月, 2021 21 次提交