This is the top USB port on the evb (the one closest to the Ethernet
connector).
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

rk3288 has two kind of usb controller; this adds the ehci variant for
host0 and hsic.

At the moment we don't add any phys for these controllers, but the
default settings seem to work OK.

There is a hardware problem in ohci controller which make it
unavailable and host0 controller can only support high-speed devices.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

There is no phy driver that works on the Rockchip board for either USB
host port yet.  For now just hardcode the vbus signal to be on all the
time which makes both the dwc2 host and the EHCI port work.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Working on sound support I noticed the Apalis T30 Evaluation board
device tree missing the more generic Apalis T30 compatible string.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Indentation of the clock property used a hodgepodge of tabs and spaces.
Make them more consistent (tabs for indentation followed by spaces for
alignment).
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This adds the Designware compatible watchdog found on RK3xxx Cortex-A9 SoCs.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We set default pinctrl settings for the uarts in rk3188.dtsi already,
so remove forgotten duplicate.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add missing pinctrl for uart0/1 for Exynos3250. The gpio pin (
uart0_data, uart0_fctl, uart1_data) is only used for UART IP.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch removes duplicat 'interrupt-parent' property for Exynos3250
because exynos3250.dtsi already defined 'interrupt-parent' property
as following:

In arch/arm/boot/dts/exynos3250.dtsi:

	compatible = "samsung,exynos3250";
	interrupt-parent = <&gic>;
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch add TMU (Thermal Management Unit) dt node to monitor the high
temperature for Exynos3250.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The IRQB interrupt pin of MAX77686 PMIC is connected to GPX3[2] pin of
Exynos5250 on the Exynos5250 SMDK board. Specify this connection using
interrupts property for the max77686 pmic node.
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Move it from exynos5250-cros-common.dtsi to exynos5250-snow.dts.
Spring does not need it, it uses an Atmel maXTouch instead.
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Move it from exynos5250-cros-common.dtsi to exynos5250-snow.dts.
Spring does not need it, it uses an s5m8767 instead.
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The DMA engine is enabled for all DTs that derive from zynq-7000.dtsi.
There is no need to override the 'status' property in board DTs.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add node describing Zynq's CAN controller.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

Adds PMU DT node for exynos5260 SoC.
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Exynos initialization code now relies on obtaining the PMU address,
so prepare a PMU node for Exynos5410.

Fixes: fce9e5bb ("ARM: EXYNOS: Add support for mapping PMU base
address via DT")
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add a sample DTS which will allow bootup of a board populated
with the BCM7445 chip.
Signed-off-by: NMarc Carino <marc.ceeeee@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Cc: Matt Porter <mporter@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

The Lenovo Iomega ix4-300d is a 4-Bay sata NAS with dual Gb, USB2.0 & 3.0,
powered by a Marvell Armada XP MV78230 dual core CPU.

http://shop.lenovo.com/us/en/servers/network-storage/lenovoemc/ix4-300d/Signed-off-by: NBenoit Masson <yahoo@perenite.com>
Link: https://lkml.kernel.org/r/1406503839-4662-1-git-send-email-yahoo@perenite.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Define nodes representing the two Cortex A9 CPUs in a bcm21644 SoC.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Define nodes representing the two Cortex A9 CPUs in a bcm28155 SoC.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMatt Porter <mporter@linaro.org>

Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This adds a device tree node for the infrared receiver connected to a
GPIO pin on the Radxa Rock.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This adds the necessary nodex and pinctrl settings for the Rockchip PWM-driver.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>

Modified to use the new clock defines and added rk3066 pins.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use the newly ammended dw_8250 clock binding to define both the baudclk as
well as the pclk supplying the ip.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Radxa Rock contains one sd-card slot. Add the supplying regulator
and enable its dw_mmc node.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This enables the 2nd i2c bus and adds the act8846 pmic as device.
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Curie2 uses a tps659102 as its main pmic, so add the i2c1 and tps65910
node as well as define the used voltages and regulator-names according to
the schematics.

Also fix the supply of the sd0 regulator, as it is supplied by the vio reg.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The core controller settings themself are identical, only the compatible and
pinctrl settings differ.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

To create some sort of ordering of nodes, they are suggested to be ordered by
their register address.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The pincontroller uses the GRF and PMU syscons nowadays, so should not
contain an address in its device node.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Use the handles for subsequent changes to nodes, similar to like the rk3288
submission does it.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Some nodes that are changed in the dtsi hierarchy do not have handles yet.
As it was suggested in the rk3288 submission to do subsequent nodes changes
through such handle-references, add the missing ones.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Comments received from the rk3288 submission indicated that a generic subnode
to group soc components should not be used.

So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The clock and reset unit is now provided by the rk3188-cru clock driver and thus
the old style definitions of the gate clocks can go away.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

The clock definitions get a lot shorter due to the soc clocks being handled by
rk3188-cru and only the input clock remains. These can now simply live
in the main rk3xxx.dtsi without affecting readability.

At the same time, rename the node to oscillator, adding a clock-output-names
property to match how the rk3288 handles this.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

This adds a node for the clock and reset unit on rk3188 and rk3066 SoCs and
also updates the device nodes retrieve their clocks from there, instead of
the previous gate clock nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-By: NMax Schwarz <max.schwarz@online.de>
Tested-By: NMax Schwarz <max.schwarz@online.de>

This allows the "make dtbs" target to work.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>

There exist 2 variants using either the act8846 or rk808 as pmic, while the
rest of the board stays the same.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Node definitions shared by all rk3288 based boards.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>