1. 03 7月, 2018 1 次提交
    • X
      mmc: dw_mmc: fix card threshold control configuration · 7a6b9f4d
      x00270170 提交于
      Card write threshold control is supposed to be set since controller
      version 2.80a for data write in HS400 mode and data read in
      HS200/HS400/SDR104 mode. However the current code returns without
      configuring it in the case of data writing in HS400 mode.
      Meanwhile the patch fixes that the current code goes to
      'disable' when doing data reading in HS400 mode.
      
      Fixes: 7e4bf1bc ("mmc: dw_mmc: add the card write threshold for HS400 mode")
      Signed-off-by: NQing Xia <xiaqing17@hisilicon.com>
      Cc: stable@vger.kernel.org # v4.8+
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      7a6b9f4d
  2. 02 5月, 2018 1 次提交
    • S
      mmc: dw_mmc: update actual clock for mmc debugfs · ff178981
      Shawn Lin 提交于
      Respect the actual clock for mmc debugfs to help better debug
      the hardware.
      
      mmc_host mmc0: Bus speed (slot 0) = 135475200Hz (slot req 150000000Hz,
      actual 135475200HZ div = 0)
      
      cat /sys/kernel/debug/mmc0/ios
      clock:          150000000 Hz
      actual clock:   135475200 Hz
      vdd:            21 (3.3 ~ 3.4 V)
      bus mode:       2 (push-pull)
      chip select:    0 (don't care)
      power mode:     2 (on)
      bus width:      3 (8 bits)
      timing spec:    9 (mmc HS200)
      signal voltage: 0 (1.80 V)
      driver type:    0 (driver type B)
      
      Cc: Xiao Yao <xiaoyao@rock-chips.com>
      Cc: Ziyuan <xzy.xu@rock-chips.com>
      Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      ff178981
  3. 16 3月, 2018 1 次提交
    • E
      mmc: dw_mmc: fix falling from idmac to PIO mode when dw_mci_reset occurs · 47b7de2f
      Evgeniy Didin 提交于
      It was found that in IDMAC mode after soft-reset driver switches
      to PIO mode.
      
      That's what happens in case of DTO timeout overflow calculation failure:
      1. soft-reset is called
      2. driver restarts dma
      3. descriptors states are checked, one of descriptor is owned by the IDMAC.
      4. driver can't use DMA and then switches to PIO mode.
      
      Failure was already fixed in:
      https://www.spinics.net/lists/linux-mmc/msg48125.html.
      
      Behaviour while soft-reset is not something we except or
      even want to happen. So we switch from dw_mci_idmac_reset
      to dw_mci_idmac_init, so descriptors are cleaned before starting dma.
      
      And while at it explicitly zero des0 which otherwise might
      contain garbage as being allocated by dmam_alloc_coherent().
      Signed-off-by: NEvgeniy Didin <Evgeniy.Didin@synopsys.com>
      Cc: Jaehoon Chung <jh80.chung@samsung.com>
      Cc: Ulf Hansson <ulf.hansson@linaro.org>
      Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
      Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
      Cc: Shawn Lin <shawn.lin@rock-chips.com>
      Cc: Alexey Brodkin <abrodkin@synopsys.com>
      Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
      Cc: linux-snps-arc@lists.infradead.org
      Cc: <stable@vger.kernel.org> # 4.4+
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      47b7de2f
  4. 15 3月, 2018 2 次提交
  5. 05 3月, 2018 3 次提交
  6. 27 2月, 2018 3 次提交
  7. 02 11月, 2017 2 次提交
    • K
      mmc: dw_mmc: Convert timers to use timer_setup() · 37977729
      Kees Cook 提交于
      In preparation for unconditionally passing the struct timer_list pointer to
      all timer callbacks, switch to using the new timer_setup() and from_timer()
      to pass the timer pointer explicitly.
      
      Cc: Jaehoon Chung <jh80.chung@samsung.com>
      Cc: Ulf Hansson <ulf.hansson@linaro.org>
      Cc: linux-mmc@vger.kernel.org
      Signed-off-by: NKees Cook <keescook@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      37977729
    • D
      mmc: dw_mmc: Cleanup the DTO timer like the CTO one · 93c23ae3
      Douglas Anderson 提交于
      The recent CTO timer introduced in commit 03de1921 ("mmc: dw_mmc:
      introduce timer for broken command transfer over scheme") was causing
      observable problems due to race conditions.  Previous patches have
      fixed those race conditions.
      
      It can be observed that these same race conditions ought to be
      theoretically possible with the DTO timer too though they are
      massively less likely to happen because the data timeout is always set
      to 0xffffff right now.  That means even at a 200 MHz card clock we
      were arming the DTO timer for 94 ms:
        >>> (0xffffff * 1000. / 200000000) + 10
        93.886075
      
      We always also were setting the DTO timer _after_ starting the
      transfer, unlike how the old code was seting the CTO timer.
      
      In any case, even though the DTO timer is much less likely to have
      races, it still makes sense to add code to handle it _just in case_.
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      93c23ae3
  8. 01 11月, 2017 1 次提交
    • D
      mmc: dw_mmc: Fix the DTO timeout calculation · 9d9491a7
      Douglas Anderson 提交于
      Just like the CTO timeout calculation introduced recently, the DTO
      timeout calculation was incorrect.  It used "bus_hz" but, as far as I
      can tell, it's supposed to use the card clock.  Let's account for the
      div value, which is documented as 2x the value stored in the register,
      or 1 if the register is 0.
      
      NOTE: This was likely not terribly important until commit 16a34574
      ("mmc: dw_mmc: remove the quirks flags") landed because "DIV" is
      documented on Rockchip SoCs (the ones that used to define the quirk)
      to always be 0 or 1.  ...and, in fact, it's documented to only be 1
      with EMMC in 8-bit DDR52 mode.  Thus before the quirk was applied to
      everyone it was mostly OK to ignore the DIV value.
      
      I haven't personally observed any problems that are fixed by this
      patch but I also haven't tested this anywhere with a DIV other an 0.
      AKA: this problem was found simply by code inspection and I have no
      failing test cases that are fixed by it.  Presumably this could fix
      real bugs for someone out there, though.
      
      Fixes: 16a34574 ("mmc: dw_mmc: remove the quirks flags")
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      9d9491a7
  9. 30 10月, 2017 5 次提交
    • D
      mmc: dw_mmc: Add locking to the CTO timer · 8892b705
      Douglas Anderson 提交于
      This attempts to instill a bit of paranoia to the code dealing with
      the CTO timer.  It's believed that this will make the CTO timer more
      robust in the case that we're having very long interrupt latencies.
      
      Note that I originally thought that perhaps this patch was being
      overly paranoid and wasn't really needed, but then while I was running
      mmc_test on an rk3399 board I saw one instance of the message:
        dwmmc_rockchip fe320000.dwmmc: Unexpected interrupt latency
      
      I had debug prints in the CTO timer code and I found that it was
      running CMD 13 at the time.
      
      ...so even though this patch seems like it might be overly paranoid,
      maybe it really isn't?
      
      Presumably the bad interrupt latency experienced was due to the fact
      that I had serial console enabled as serial console is typically where
      I place blame when I see absurdly large interrupt latencies.  In this
      particular case there was an (unrelated) printout to the serial
      console just before I saw the "Unexpected interrupt latency" printout.
      
      ...and actually, I managed to even reproduce the problems by running
      "iw mlan0 scan > /dev/null" while mmc_test was running.  That not only
      does a bunch of PCIe traffic but it also (on my system) outputs some
      SELinux log spam.
      
      Fixes: 03de1921 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme")
      Tested-by: NEmil Renner Berthing <kernel@esmil.dk>
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      8892b705
    • D
      mmc: dw_mmc: Fix the CTO timeout calculation · 4c2357f5
      Douglas Anderson 提交于
      In the commit 03de1921 ("mmc: dw_mmc: introduce timer for broken
      command transfer over scheme") we tried to calculate the expected
      hardware command timeout value.  Unfortunately that calculation isn't
      quite correct in all cases.  It used "bus_hz" but, as far as I can
      tell, it's supposed to use the card clock.  Let's account for the div
      value, which is documented as 2x the value stored in the register, or
      1 if the register is 0.
      
      NOTE: It's not expected that this will actually fix anything important
      since the 10 ms margin added by the function will pretty much dwarf
      any calculations.  The card clock should be 100 kHz at minimum and:
        1000 ms/s * (255 * 2) / 100000 Hz.
      Gives us 5.1 ms.
      
      ...so really the point of this patch is just to make the code more
      "correct" in case anyone ever tries to remove the 10 ms buffer.
      
      Fixes: 03de1921 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme")
      Tested-by: NEmil Renner Berthing <kernel@esmil.dk>
      Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      4c2357f5
    • D
      mmc: dw_mmc: cancel the CTO timer after a voltage switch · 0363b12d
      Douglas Anderson 提交于
      When running with the commit 03de1921 ("mmc: dw_mmc: introduce
      timer for broken command transfer over scheme") I found this message
      in the log:
        Unexpected command timeout, state 7
      
      It turns out that we weren't properly cancelling the new CTO timer in
      the case that a voltage switch was done.  Let's promote the cancel
      into the dw_mci_cmd_interrupt() function to fix this.
      
      Fixes: 03de1921 ("mmc: dw_mmc: introduce timer for broken command transfer over scheme")
      Tested-by: NEmil Renner Berthing <kernel@esmil.dk>
      Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
      Signed-off-by: NDouglas Anderson <dianders@chromium.org>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      0363b12d
    • W
      mmc: dw_mmc: catch all errors when getting regulators · 0f3a47b8
      Wolfram Sang 提交于
      Bail out everytime when mmc_regulator_get_supply() returns an errno, not
      only when probing gets deferred. This is currently a no-op, because this
      function only returns -EPROBE_DEFER or 0 right now. But if it will throw
      another error somewhen, it will be for a reason. (This still doesn't change
      that getting regulators is optional, so 0 can still mean no regulators
      found). So, let us a) be future proof and b) have driver code which is
      easier to understand.
      Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      0f3a47b8
    • C
      mmc: dw_mmc: make const arrays mszs static · 27d70d36
      Colin Ian King 提交于
      Don't populate the const arrays mszs on the stack, instead make them
      static. Makes the object code smaller by over 310 bytes:
      
      Before:
         text	   data	    bss	    dec	    hex	filename
        47527	   8528	    320	  56375	   dc37	drivers/mmc/host/dw_mmc.o
      
      After:
         text	   data	    bss	    dec	    hex	filename
        47055	   8688	    320	  56063	   daff	drivers/mmc/host/dw_mmc.o
      Signed-off-by: NColin Ian King <colin.king@canonical.com>
      Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      27d70d36
  10. 30 8月, 2017 3 次提交
  11. 27 7月, 2017 1 次提交
  12. 29 6月, 2017 6 次提交
  13. 20 6月, 2017 4 次提交
  14. 25 4月, 2017 7 次提交