Skip to content

K
Kernel

openeuler / Kernel
1 年多 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 19 3月, 2014 1 次提交
  3. 04 12月, 2013 1 次提交
  5. 22 8月, 2013 2 次提交
    • S
      spi/qspi: Add qspi flash controller · 505a1495
      由 Sourav Poddar 提交于 
      The patch add basic support for the quad spi controller.

QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.

The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).

Test details:
-------------
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 40000 iterations.
   - All iterations went through without failure.
Test2: Use mtd utilities:
  - flash_erase to erase the flash device
  - mtd_debug read to read data back.
  - mtd_debug write to write to the data flash.
 diff between the write and read data shows zero.

Acked-by: Felipe Balbi<balbi@ti.com>
Reviewed-by: Felipe Balbi<balbi@ti.com>
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NMark Brown <broonie@linaro.org>
      505a1495
    • C
      spi:Add Freescale DSPI driver for Vybrid VF610 platform · 349ad66c
      由 Chao Fu 提交于 
      The serial peripheral interface (SPI) module implemented on Freescale Vybrid
platform provides a synchronous serial bus for communication between Vybrid
and the external peripheral device.
The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO
with depth of four entries.

This driver is the SPI master mode driver and has been tested on Vybrid
VF610TWR board.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NChao Fu  <b44548@freescale.com>
Signed-off-by: NMark Brown <broonie@linaro.org>
      349ad66c
  7. 10 8月, 2013 1 次提交
  9. 15 7月, 2013 1 次提交
  11. 07 4月, 2013 2 次提交
  13. 13 3月, 2013 1 次提交
    • C
      spi: add driver for BCM2835 · f8043872
      由 Chris Boot 提交于 
      The BCM2835 contains two forms of SPI master controller (one known
simply as SPI0, and the other known as the "Universal SPI Master", in
the auxilliary block) and one form of SPI slave controller. This patch
adds support for the SPI0 controller.

This driver is taken from Chris Boot's repository at
git://github.com/bootc/linux.git rpi-linear
as of commit 6de2905 "spi-bcm2708: fix printf with spurious %s".
In the first SPI-related commit there, Chris wrote:

Thanks to csoutreach / A Robinson for his driver which I used as an
inspiration. You can find his version here:
http://piface.openlx.org.uk/raspberry-pi-spi-kernel-driver-available-for

Changes made during upstreaming:
* Renamed bcm2708 to bcm2835 as per upstream naming for this SoC.
* Removed support for brcm,realtime property.
* Increased transfer timeout to 30 seconds.
* Return IRQ_NONE from the IRQ handler if no interrupt was handled.
* Disable TA (Transfer Active) and clear FIFOs on a transfer timeout.
* Wrote device tree binding documentation.
* Request unnamed clock rather than "sys_pclk"; the DT will provide the
  correct clock.
* Assume that tfr->speed_hz and tfr->bits_per_word are always set in
  bcm2835_spi_start_transfer(), bcm2835_spi_transfer_one(), so no need
  to check spi->speed_hz or tft->bits_per_word.
* Re-ordered probe() to remove the need for temporary variables.
* Call clk_disable_unprepare() rather than just clk_unprepare() on probe()
  failure.
* Don't use devm_request_irq(), to ensure that the IRQ doesn't fire after
  we've torn down the device, but not unhooked the IRQ.
* Moved probe()'s call to clk_prepare_enable() so we can be sure the clock
  is enabled if the IRQ handler fires immediately.
* Remove redundant checks from bcm2835_spi_check_transfer() and
  bcm2835_spi_setup().
* Re-ordered IRQ handler to check for RXR before DONE. Added comments to
  ISR.
* Removed empty prepare/unprepare implementations.
* Removed use of devinit/devexit.
* Added BCM2835_ prefix to defines.
Signed-off-by: NChris Boot <bootc@bootc.net>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      f8043872
  15. 08 2月, 2013 2 次提交
  17. 06 12月, 2012 2 次提交
  19. 14 11月, 2012 1 次提交
  21. 31 10月, 2012 1 次提交
  23. 01 10月, 2012 1 次提交
    • S
      spi: remove completely broken Tegra driver · 536a53a3
      由 Stephen Warren 提交于 
      The current SPI driver has many issues. Examples are:

* Segfaulting on most transfers due to expecting all transfers to have
  both RX and TX buffers.
* Hanging on TX transfers since the whole driver flow is driven by RX
  DMA completion, but the HW is only told to enable RX for RX transfers.
* Use of clk_disable_unprepare() from atomic context.
* Once those and other minor issues are fixed, the driver still doesn't
  actually work.
* The driver also implements a deprecated API to the SPI core.

For this reason, simply remove the driver completely. This has two
advantages:

1) This will remove the last use of Tegra's <mach/dma.h>, which will
   allow that file to be removed, which is required for single zImage
   work.

2) The downstream driver is significaly different from the current
   code. I believe a patch to re-add the downstream driver (with
   appropriate cleanup) will be much simpler to review if it's a new
   file rather than randomly interspered with essentially unrelated
   existing code.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      536a53a3
  25. 23 8月, 2012 2 次提交
  27. 18 8月, 2012 1 次提交
  29. 23 7月, 2012 1 次提交
  31. 20 7月, 2012 1 次提交
  33. 28 4月, 2012 1 次提交
  35. 10 3月, 2012 3 次提交
  37. 08 3月, 2012 1 次提交
  39. 05 7月, 2011 1 次提交
  41. 06 6月, 2011 1 次提交
  43. 27 5月, 2011 1 次提交
  45. 15 3月, 2011 1 次提交
  47. 23 2月, 2011 3 次提交
  49. 19 1月, 2011 1 次提交
  51. 24 12月, 2010 1 次提交
  53. 01 12月, 2010 1 次提交
  55. 10 11月, 2010 2 次提交
  57. 22 10月, 2010 1 次提交
    • E
      spi: add spi_tegra driver · 0c03a1dd
      由 Erik Gilling 提交于 
      v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1
Signed-off-by: NErik Gilling <konkers@android.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: NErik Gilling <konkers@android.com>
      0c03a1dd
  59. 13 10月, 2010 1 次提交
    • M
      spi/fsl_spi: add eSPI controller support · 8b60d6c2
      由 Mingkai Hu 提交于 
      Add eSPI controller support based on the library code spi_fsl_lib.c.

The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:

1. Has different register map and different bit definition
   So leave the code operated the register to the driver code, not
   the common code.

2. Support 4 dedicated chip selects
   The software can't controll the chip selects directly, The SPCOM[CS]
   field is used to select which chip selects is used, and the
   SPCOM[TRANLEN] field is set to tell the controller how long the CS
   signal need to be asserted. So the driver doesn't need the chipselect
   related function when transfering data, just set corresponding register
   fields to controll the chipseclect.

3. Different Transmit/Receive FIFO access register behavior
   For SPI controller, the Tx/Rx FIFO access register can hold only
   one character regardless of the character length, but for eSPI
   controller, the register can hold 4 or 2 characters according to
   the character lengths. Access the Tx/Rx FIFO access register of the
   eSPI controller will shift out/in 4/2 characters one time. For SPI
   subsystem, the command and data are put into different transfers, so
   we need to combine all the transfers to one transfer in order to pass
   the transfer to eSPI controller.

4. The max transaction length limitation
   The max transaction length one time is limitted by the SPCOM[TRANSLEN]
   field which is 0xFFFF. When used mkfs.ext2 command to create ext2
   filesystem on the flash, the read length will exceed the max value of
   the SPCOM[TRANSLEN] field.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      8b60d6c2